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Finish CPU implementation

master
Forest Belton 3 years ago
parent
commit
3f317e4c9f
2 changed files with 34 additions and 10 deletions
  1. +21
    -10
      gbso/cpu.py
  2. +13
    -0
      gbso/regs.py

+ 21
- 10
gbso/cpu.py View File

@ -1,35 +1,46 @@
from gbso.regs import R8, R16
from collections import defaultdict
from typing import Dict
from gbso.regs import R16_HI, R16_LO, R8, R16
class CPU:
carry: int
cycles: int
reg8: Dict[R8, int]
memory: bytearray
def __init__(self) -> None:
self.carry = 0
self.cycles = 0
self.reg8 = defaultdict(lambda: 0)
self.memory = bytearray(0xFFFF + 1)
def get_reg8(self, r: R8) -> int:
pass
returnn> <span class="bp">self.reg8[r]
def get_reg16(self, rr: R16) -> int:
pass
returnn> <span class="p">(self.reg8[R16_HI[rr]] << 8) | self.reg8[R16_LO[rr]]
def set_reg8(self, r: R8, n: int) -> None:
pass
self.reg8[r] = n & 0xFF
def set_reg16(self, r: R16, nn: int) -> None:
pass
def set_reg16(self, rr: R16, nn: int) -> None:
self.reg8[R16_HI[rr]] = (nn >> 8) & 0xFF
self.reg8[R16_LO[rr]] = nn & 0xFF
def get_mem8(self, nn: int) -> int:
pass
returnn> <span class="bp">self.memory[nn & 0xFFFF]
def get_mem16(self, nn: int) -> int:
pass
returnn> (self.span>memory[(<span class="n">nn + 1) & 0xFF] << 8) | self.memory[nn & 0xFFFF]
def set_mem8(self, nn: int, n: int) -> None:
pass
self.memory[nn & 0xFFFF] = n & 0xFF
def set_mem16(self, nn: int, nn1: int) -> None:
pass
self.memory[nn & 0xFFFF] = nn1 & 0xFF
self.memory[(nn + 1) & 0xFFFF] = (nn1 >> 8) & 0xFF
def deref_hl(self) -> int:
return self.get_mem8(self.get_reg16(R16.HL))

+ 13
- 0
gbso/regs.py View File

@ -17,3 +17,16 @@ class R16(Enum):
DE = "DE"
HL = "HL"
SP = "SP"
R16_HI = {
R16.BC: R8.B,
R16.DE: R8.D,
R16.HL: R8.H,
}
R16_LO = {
R16.BC: R8.C,
R16.DE: R8.E,
R16.HL: R8.L,
}

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