From 57fe6b9a292057124c59d64adf85dd1018a89e00 Mon Sep 17 00:00:00 2001 From: Forest Belton <65484+forestbelton@users.noreply.github.com> Date: Sun, 25 Jul 2021 00:46:50 -0400 Subject: [PATCH] Finish rotate & shift tests --- gbso/insn.py | 8 ++ tests/insn/test_shift.py | 207 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 214 insertions(+), 1 deletion(-) diff --git a/gbso/insn.py b/gbso/insn.py index 440a7da..0f061bf 100644 --- a/gbso/insn.py +++ b/gbso/insn.py @@ -902,6 +902,7 @@ class SLA_R(Insn): def exec(self, cpu: CPU) -> None: r = cpu.get_reg8(self.r) + cpu.carry = 1 if r & (1 << 7) else 0 cpu.set_reg8(self.r, (r << 1) & 0xFF) cpu.cycles += 8 @@ -913,6 +914,7 @@ class SLA_R(Insn): class SLA_HL(Insn): def exec(self, cpu: CPU) -> None: hl = cpu.deref_hl() + cpu.carry = 1 if hl & (1 << 7) else 0 cpu.deref_hl_set((hl << 1) & 0xFF) cpu.cycles += 16 @@ -927,6 +929,7 @@ class SWAP_R(Insn): def exec(self, cpu: CPU) -> None: r = cpu.get_reg8(self.r) cpu.set_reg8(self.r, ((r << 4) & 0xFF) | (r >> 4)) + cpu.carry = 0 cpu.cycles += 8 def pretty(self) -> str: @@ -938,6 +941,7 @@ class SWAP_HL(Insn): def exec(self, cpu: CPU) -> None: hl = cpu.deref_hl() cpu.deref_hl_set(((hl << 4) & 0xFF) | (hl >> 4)) + cpu.carry = 0 cpu.cycles += 16 def pretty(self) -> str: @@ -950,6 +954,7 @@ class SRA_R(Insn): def exec(self, cpu: CPU) -> None: r = cpu.get_reg8(self.r) + cpu.carry = 1 if r & (1 << 0) else 0 cpu.set_reg8(self.r, (r >> 1) | (r & (1 << 7))) cpu.cycles += 8 @@ -961,6 +966,7 @@ class SRA_R(Insn): class SRA_HL(Insn): def exec(self, cpu: CPU) -> None: hl = cpu.deref_hl() + cpu.carry = 1 if hl & (1 << 0) else 0 cpu.deref_hl_set((hl >> 1) | (hl & (1 << 7))) cpu.cycles += 16 @@ -974,6 +980,7 @@ class SRL_R(Insn): def exec(self, cpu: CPU) -> None: r = cpu.get_reg8(self.r) + cpu.carry = 1 if r & (1 << 0) else 0 cpu.set_reg8(self.r, r >> 1) cpu.cycles += 8 @@ -985,6 +992,7 @@ class SRL_R(Insn): class SRL_HL(Insn): def exec(self, cpu: CPU) -> None: hl = cpu.deref_hl() + cpu.carry = 1 if hl & (1 << 0) else 0 cpu.deref_hl_set(hl >> 1) cpu.cycles += 16 diff --git a/tests/insn/test_shift.py b/tests/insn/test_shift.py index 35680d0..bbc2b91 100644 --- a/tests/insn/test_shift.py +++ b/tests/insn/test_shift.py @@ -89,6 +89,23 @@ def test_rlc_r(r): assert cpu.cycles == 16 +def test_rlc_hl(): + cpu = CPU() + cpu.deref_hl_set(0x80) + + RLC_HL().exec(cpu) + + assert cpu.deref_hl() == 0x01 + assert cpu.carry == 1 + assert cpu.cycles == 16 + + RLC_HL().exec(cpu) + + assert cpu.deref_hl() == 0x02 + assert cpu.carry == 0 + assert cpu.cycles == 32 + + @pytest.mark.parametrize("r", R8) def test_rl_r(r): cpu = CPU() @@ -107,6 +124,23 @@ def test_rl_r(r): assert cpu.cycles == 16 +def test_rl_hl(): + cpu = CPU() + cpu.deref_hl_set(0x80) + + RL_HL().exec(cpu) + + assert cpu.deref_hl() == 0x00 + assert cpu.carry == 1 + assert cpu.cycles == 16 + + RL_HL().exec(cpu) + + assert cpu.deref_hl() == 0x01 + assert cpu.carry == 0 + assert cpu.cycles == 32 + + @pytest.mark.parametrize("r", R8) def test_rrc_r(r): cpu = CPU() @@ -125,6 +159,24 @@ def test_rrc_r(r): assert cpu.cycles == 16 +def test_rrc_hl(): + cpu = CPU() + cpu.set_reg16(R16.HL, 0x1234) + cpu.deref_hl_set(0x01) + + RRC_HL().exec(cpu) + + assert cpu.deref_hl() == 0x80 + assert cpu.carry == 1 + assert cpu.cycles == 16 + + RRC_HL().exec(cpu) + + assert cpu.deref_hl() == 0x40 + assert cpu.carry == 0 + assert cpu.cycles == 32 + + @pytest.mark.parametrize("r", R8) def test_rr_r(r): cpu = CPU() @@ -143,4 +195,157 @@ def test_rr_r(r): assert cpu.cycles == 16 -# TODO: Test RLC_HL, RL_HL, RRC_HL, RR_HL +def test_rr_hl(): + cpu = CPU() + cpu.set_reg16(R16.HL, 0x1234) + cpu.deref_hl_set(0x01) + + RR_HL().exec(cpu) + + assert cpu.deref_hl() == 0x00 + assert cpu.carry == 1 + assert cpu.cycles == 16 + + RR_HL().exec(cpu) + + assert cpu.deref_hl() == 0x80 + assert cpu.carry == 0 + assert cpu.cycles == 32 + + +@pytest.mark.parametrize("r", R8) +def test_sla_r(r): + cpu = CPU() + cpu.set_reg8(r, 0xFF) + + SLA_R(r).exec(cpu) + + assert cpu.get_reg8(r) == 0xFE + assert cpu.carry == 1 + assert cpu.cycles == 8 + + cpu.set_reg8(r, 0x01) + SLA_R(r).exec(cpu) + + assert cpu.get_reg8(r) == 0x02 + assert cpu.carry == 0 + assert cpu.cycles == 16 + + +def test_sla_hl(): + cpu = CPU() + cpu.set_reg16(R16.HL, 0x1234) + cpu.deref_hl_set(0xFF) + + SLA_HL().exec(cpu) + + assert cpu.deref_hl() == 0xFE + assert cpu.carry == 1 + assert cpu.cycles == 16 + + cpu.deref_hl_set(0x01) + SLA_HL().exec(cpu) + + assert cpu.deref_hl() == 0x02 + assert cpu.carry == 0 + assert cpu.cycles == 32 + + +@pytest.mark.parametrize("r", R8) +def test_swap_r(r): + cpu = CPU() + cpu.set_reg8(r, 0xAB) + + SWAP_R(r).exec(cpu) + + assert cpu.get_reg8(r) == 0xBA + assert cpu.carry == 0 + assert cpu.cycles == 8 + + +def test_swap_hl(): + cpu = CPU() + cpu.set_reg16(R16.HL, 0x1234) + cpu.deref_hl_set(0xAB) + + SWAP_HL().exec(cpu) + + assert cpu.deref_hl() == 0xBA + assert cpu.carry == 0 + assert cpu.cycles == 16 + + +@pytest.mark.parametrize("r", R8) +def test_sra_r(r): + cpu = CPU() + cpu.set_reg8(r, 0xFF) + + SRA_R(r).exec(cpu) + + assert cpu.get_reg8(r) == 0xFF + assert cpu.carry == 1 + assert cpu.cycles == 8 + + cpu.set_reg8(r, 0x02) + SRA_R(r).exec(cpu) + + assert cpu.get_reg8(r) == 0x01 + assert cpu.carry == 0 + assert cpu.cycles == 16 + + +def test_sra_hl(): + cpu = CPU() + cpu.set_reg16(R16.HL, 0x1234) + cpu.deref_hl_set(0xFF) + + SRA_HL().exec(cpu) + + assert cpu.deref_hl() == 0xFF + assert cpu.carry == 1 + assert cpu.cycles == 16 + + cpu.deref_hl_set(0x02) + SRA_HL().exec(cpu) + + assert cpu.deref_hl() == 0x01 + assert cpu.carry == 0 + assert cpu.cycles == 32 + + +@pytest.mark.parametrize("r", R8) +def test_srl_r(r): + cpu = CPU() + cpu.set_reg8(r, 0xFF) + + SRL_R(r).exec(cpu) + + assert cpu.get_reg8(r) == 0x7F + assert cpu.carry == 1 + assert cpu.cycles == 8 + + cpu.set_reg8(r, 0x02) + SRL_R(r).exec(cpu) + + assert cpu.get_reg8(r) == 0x01 + assert cpu.carry == 0 + assert cpu.cycles == 16 + + +def test_srl_hl(): + cpu = CPU() + cpu.set_reg16(R16.HL, 0x1234) + cpu.deref_hl_set(0xFF) + + SRL_HL().exec(cpu) + + assert cpu.deref_hl() == 0x7F + assert cpu.carry == 1 + assert cpu.cycles == 16 + + cpu.deref_hl_set(0x02) + SRL_HL().exec(cpu) + + assert cpu.deref_hl() == 0x01 + assert cpu.carry == 0 + assert cpu.cycles == 32