Initial commit

.gitignore

@@ -0,0 +1 @@
+__pycache__/

ex.py

@@ -0,0 +1,24 @@
+from gbso.insn import *
+from gbso.optimize import optimize
+from gbso.program import Program
+from gbso.regs import R8, R16
+
+rLCDC = 0xFF40
+rIE = 0xFFFF
+
+IEF_VBLANK = 1 << 0
+
+prgm = Program(
+    outputs=set([R8.A]),
+    insns=[
+        LD_RR_NN(R16.HL, rLCDC),
+        RES_N_HL(7),
+        RES_N_HL(2),
+        LD_RR_NN(R16.HL, rIE),
+        LD_HL_N(IEF_VBLANK),
+    ],
+)
+
+prgm_opt = optimize(prgm)
+for insn in prgm_opt.insns:
+    print(insn.pretty())

gbso/__init__.py

@@ -0,0 +1 @@
+__version__ = '0.1.0'

gbso/cpu.py

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+from gbso.regs import R8, R16
+
+
+class CPU:
+    carry: int
+
+    def __init__(self) -> None:
+        self.carry = 0
+
+    def get_reg8(self, r: R8) -> int:
+        pass
+
+    def get_reg16(self, rr: R16) -> int:
+        pass
+
+    def set_reg8(self, r: R8, n: int) -> None:
+        pass
+
+    def set_reg16(self, r: R16, nn: int) -> None:
+        pass
+
+    def get_mem8(self, nn: int) -> int:
+        pass
+
+    def get_mem16(self, nn: int) -> int:
+        pass
+
+    def set_mem8(self, nn: int, n: int) -> None:
+        pass
+
+    def set_mem16(self, nn: int, nn1: int) -> None:
+        pass

gbso/insn.py

@@ -0,0 +1,576 @@
+from abc import ABC, abstractmethod
+from dataclasses import dataclass
+
+from gbso.cpu import CPU
+from gbso.regs import R16, R8
+
+
+class Insn(ABC):
+    @abstractmethod
+    def exec(self, cpu: CPU) -> None:
+        pass
+
+    # TODO: Make abstract once all subclasses implement
+    def pretty(self) -> str:
+        return ""
+
+
+@dataclass
+class LD_R_R(Insn):
+    dst: R8
+    src: R8
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(self.dst, cpu.get_reg8(self.src))
+
+    def pretty(self) -> str:
+        return f"LD {self.dst}, {self.src}"
+
+
+@dataclass
+class LD_R_N8(Insn):
+    dst: R8
+    imm: int
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(self.dst, self.imm)
+
+
+@dataclass
+class LD_R_HL(Insn):
+    dst: R8
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(self.dst, cpu.get_mem8(cpu.get_reg16(R16.HL)))
+
+
+@dataclass
+class LD_HL_R(Insn):
+    src: R8
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_mem8(cpu.get_reg16(R16.HL), cpu.get_reg8(self.src))
+
+
+@dataclass
+class LD_HL_N(Insn):
+    imm: int
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_mem8(cpu.get_reg16(R16.HL), self.imm)
+
+    def pretty(self) -> str:
+        return f"LD (HL), {hex(self.imm & 0xff)}"
+
+
+@dataclass
+class LD_A_BC(Insn):
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(R8.A, cpu.get_mem8(cpu.get_reg16(R16.BC)))
+
+
+@dataclass
+class LD_A_DE(Insn):
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(R8.A, cpu.get_mem8(cpu.get_reg16(R16.DE)))
+
+
+@dataclass
+class LD_A_NN(Insn):
+    nn: int
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(R8.A, cpu.get_mem8(self.nn))
+
+
+@dataclass
+class LD_BC_A(Insn):
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_mem8(cpu.get_reg16(R16.BC), cpu.get_reg8(R8.A))
+
+
+@dataclass
+class LD_DE_A(Insn):
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_mem8(cpu.get_reg16(R16.DE), cpu.get_reg8(R8.A))
+
+
+@dataclass
+class LD_NN_A(Insn):
+    nn: int
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_mem8(self.nn, cpu.get_reg8(R8.A))
+
+
+@dataclass
+class LD_A_FF_N(Insn):
+    n: int
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(R8.A, cpu.get_mem8(0xFF00 + self.n))
+
+
+@dataclass
+class LD_FF_N_A(Insn):
+    n: int
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_mem8(0xFF00 + self.n, cpu.get_reg8(R8.A))
+
+
+@dataclass
+class LD_A_FF_C(Insn):
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(R8.A, cpu.get_mem8(0xFF00 + cpu.get_reg8(R8.C)))
+
+
+@dataclass
+class LD_FF_C_A(Insn):
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_mem8(0xFF00 + cpu.get_reg8(R8.C), cpu.get_reg8(R8.A))
+
+
+@dataclass
+class LDI_HL_A(Insn):
+    def exec(self, cpu: CPU) -> None:
+        hl = cpu.get_reg16(R16.HL)
+        cpu.set_mem8(hl, cpu.get_reg8(R8.A))
+        cpu.set_reg16(R16.HL, hl + 1)
+
+
+@dataclass
+class LDI_A_HL(Insn):
+    def exec(self, cpu: CPU) -> None:
+        hl = cpu.get_reg16(R16.HL)
+        cpu.set_reg8(R8.A, cpu.get_mem8(hl))
+        cpu.set_reg16(R16.HL, hl + 1)
+
+
+@dataclass
+class LDD_HL_A(Insn):
+    def exec(self, cpu: CPU) -> None:
+        hl = cpu.get_reg16(R16.HL)
+        cpu.set_mem8(hl, cpu.get_reg8(R8.A))
+        cpu.set_reg16(R16.HL, hl - 1)
+
+
+@dataclass
+class LDD_A_HL(Insn):
+    def exec(self, cpu: CPU) -> None:
+        hl = cpu.get_reg16(R16.HL)
+        cpu.set_reg8(R8.A, cpu.get_mem8(hl))
+        cpu.set_reg16(R16.HL, hl - 1)
+
+
+@dataclass
+class LD_RR_NN(Insn):
+    rr: R16
+    nn: int
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg16(self.rr, self.nn)
+
+    def pretty(self) -> str:
+        return f"LD {self.rr.value}, {hex(self.nn)}"
+
+
+@dataclass
+class LD_NN_SP(Insn):
+    nn: int
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_mem16(self.nn, cpu.get_reg16(R16.SP))
+
+
+@dataclass
+class LD_SP_HL(Insn):
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg16(R16.SP, cpu.get_reg16(R16.HL))
+
+
+@dataclass
+class PUSH_RR(Insn):
+    rr: R16
+
+    def exec(self, cpu: CPU) -> None:
+        sp = cpu.get_reg16(R16.SP)
+        cpu.set_reg16(R16.SP, sp - 2)
+        cpu.set_mem16(sp - 2, cpu.get_reg16(self.rr))
+
+
+@dataclass
+class POP_RR(Insn):
+    rr: R16
+
+    def exec(self, cpu: CPU) -> None:
+        sp = cpu.get_reg16(R16.SP)
+        cpu.set_reg16(self.rr, cpu.get_mem16(sp))
+        cpu.set_reg16(R16.SP, sp + 2)
+
+
+@dataclass
+class ADD_A_R(Insn):
+    r: R8
+
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) + cpu.get_reg8(self.r)
+        cpu.carry = 1 if a > 0xFF else 0
+        cpu.set_reg8(R8.A, a)
+
+
+@dataclass
+class ADD_A_N(Insn):
+    n: int
+
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) + self.n
+        cpu.carry = 1 if a > 0xFF else 0
+        cpu.set_reg8(R8.A, a)
+
+
+@dataclass
+class ADD_A_HL(Insn):
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) + cpu.get_mem8(cpu.get_reg16(R16.HL))
+        cpu.carry = 1 if a > 0xFF else 0
+        cpu.set_reg8(R8.A, a)
+
+
+@dataclass
+class ADC_A_R(Insn):
+    r: R8
+
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) + cpu.get_reg8(self.r) + cpu.carry
+        cpu.carry = 1 if a > 0xFF else 0
+        cpu.set_reg8(R8.A, a)
+
+
+@dataclass
+class ADC_A_N(Insn):
+    n: int
+
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) + self.n + cpu.carry
+        cpu.carry = 1 if a > 0xFF else 0
+        cpu.set_reg8(R8.A, a)
+
+
+@dataclass
+class ADC_A_HL(Insn):
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) + cpu.get_mem8(cpu.get_reg16(R16.HL)) + cpu.carry
+        cpu.carry = 1 if a > 0xFF else 0
+        cpu.set_reg8(R8.A, a)
+
+
+@dataclass
+class SUB_A_R(Insn):
+    r: R8
+
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) - cpu.get_reg8(self.r)
+        cpu.carry = 1 if a < 0 else 0
+        cpu.set_reg8(R8.A, a)
+
+
+@dataclass
+class SUB_A_N(Insn):
+    n: int
+
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) - self.n
+        cpu.carry = 1 if a < 0 else 0
+        cpu.set_reg8(R8.A, a)
+
+
+@dataclass
+class SUB_A_HL(Insn):
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) - cpu.get_mem8(cpu.get_reg16(R16.HL))
+        cpu.carry = 1 if a < 0 else 0
+        cpu.set_reg8(R8.A, a)
+
+
+@dataclass
+class SBC_A_R(Insn):
+    r: R8
+
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) - cpu.get_reg8(self.r) - cpu.carry
+        cpu.carry = 1 if a < 0 else 0
+        cpu.set_reg8(R8.A, a)
+
+
+@dataclass
+class SBC_A_N(Insn):
+    n: int
+
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) - self.n - cpu.carry
+        cpu.carry = 1 if a < 0 else 0
+        cpu.set_reg8(R8.A, a)
+
+
+@dataclass
+class SBC_A_HL(Insn):
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) - cpu.get_mem8(cpu.get_reg16(R16.HL)) - cpu.carry
+        cpu.carry = 1 if a < 0 else 0
+        cpu.set_reg8(R8.A, a)
+
+
+@dataclass
+class AND_A_R(Insn):
+    r: R8
+
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) & cpu.get_reg8(self.r)
+        cpu.set_reg8(R8.A, a)
+        cpu.carry = 0
+
+
+@dataclass
+class AND_A_N(Insn):
+    n: int
+
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) & self.n
+        cpu.set_reg8(R8.A, a)
+        cpu.carry = 0
+
+
+@dataclass
+class AND_A_HL(Insn):
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A) & cpu.get_mem8(cpu.get_reg16(R16.HL))
+        cpu.set_reg8(R8.A, a)
+        cpu.carry = 0
+
+
+@dataclass
+class CP_A_R(Insn):
+    r: R8
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.carry = 1 if cpu.get_reg8(R8.A) < cpu.get_reg8(self.r) else 0
+
+
+@dataclass
+class CP_A_N(Insn):
+    n: int
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.carry = 1 if cpu.get_reg8(R8.A) < self.n else 0
+
+
+@dataclass
+class CP_A_HL(Insn):
+    def exec(self, cpu: CPU) -> None:
+        cpu.carry = 1 if cpu.get_reg8(R8.A) < cpu.get_mem8(cpu.get_reg16(R16.HL)) else 0
+
+
+@dataclass
+class INC_R(Insn):
+    r: R8
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(self.r, cpu.get_reg8(self.r) + 1)
+
+
+@dataclass
+class INC_HL(Insn):
+    r: R8
+
+    def exec(self, cpu: CPU) -> None:
+        hl = cpu.get_reg16(R16.HL)
+        cpu.set_mem8(hl, cpu.get_mem8(hl) + 1)
+
+
+@dataclass
+class DEC_R(Insn):
+    r: R8
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(self.r, cpu.get_reg8(self.r) - 1)
+
+
+@dataclass
+class DEC_HL(Insn):
+    r: R8
+
+    def exec(self, cpu: CPU) -> None:
+        hl = cpu.get_reg16(R16.HL)
+        cpu.set_mem8(hl, cpu.get_mem8(hl) - 1)
+
+
+@dataclass
+class CPL(Insn):
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(R8.A, cpu.get_reg8(R8.A) ^ 0xFF)
+
+
+@dataclass
+class ADD_HL_RR(Insn):
+    rr: R16
+
+    def exec(self, cpu: CPU) -> None:
+        hl = cpu.get_reg16(R16.HL) + cpu.get_reg16(self.rr)
+        cpu.carry = 1 if hl > 0xFFFF else 0
+        cpu.set_reg16(R16.HL, hl)
+
+
+@dataclass
+class INC_RR(Insn):
+    rr: R16
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg16(self.rr, cpu.get_reg16(self.rr) + 1)
+
+    def pretty(self) -> str:
+        return f"INC {self.rr.value}"
+
+
+@dataclass
+class DEC_RR(Insn):
+    rr: R16
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg16(self.rr, cpu.get_reg16(self.rr) - 1)
+
+    def pretty(self) -> str:
+        return f"DEC {self.rr.value}"
+
+
+@dataclass
+class ADD_SP_DD(Insn):
+    dd: int
+
+    def exec(self, cpu: CPU) -> None:
+        sp = cpu.get_reg16(R16.SP) + self.dd
+        cpu.carry = 1 if sp > 0xFFFF or sp < 0 else 0
+        cpu.set_reg16(R16.SP, sp)
+
+
+@dataclass
+class LD_HL_SP_DD(Insn):
+    dd: int
+
+    def exec(self, cpu: CPU) -> None:
+        sp = cpu.get_reg16(R16.SP) + self.dd
+        cpu.carry = 1 if sp > 0xFFFF or sp < 0 else 0
+        cpu.set_reg16(R16.HL, sp)
+
+
+# TODO: Rotate and shift instructions
+@dataclass
+class RLCA(Insn):
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A)
+        cpu.carry = (a >> 7) & 1
+        cpu.set_reg8(R8.A, ((a << 1) & 0xFF) | cpu.carry)
+
+    def pretty(self) -> str:
+        return "RLCA"
+
+
+@dataclass
+class RLA(Insn):
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A)
+        next_carry = (a >> 7) & 1
+        cpu.set_reg8(R8.A, ((a << 1) & 0xFF) | cpu.carry)
+        cpu.carry = next_carry
+
+    def pretty(self) -> str:
+        return "RLA"
+
+
+@dataclass
+class RRCA(Insn):
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A)
+        cpu.carry = a & 1
+        cpu.set_reg8(R8.A, (a >> 1) | (cpu.carry << 7))
+
+    def pretty(self) -> str:
+        return "RRCA"
+
+
+@dataclass
+class RRA(Insn):
+    def exec(self, cpu: CPU) -> None:
+        a = cpu.get_reg8(R8.A)
+        next_carry = a & 1
+        cpu.set_reg8(R8.A, (a >> 1) | (cpu.carry << 7))
+        cpu.carry = next_carry
+
+    def pretty(self) -> str:
+        return "RRA"
+
+
+@dataclass
+class SET_N_R(Insn):
+    n: int
+    r: R8
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(self.r, cpu.get_reg8(self.r) | (1 << self.n))
+
+    def pretty(self) -> str:
+        return f"SET {self.n}, (HL)"
+
+
+@dataclass
+class SET_N_HL(Insn):
+    n: int
+
+    def exec(self, cpu: CPU) -> None:
+        hl = cpu.get_reg16(R16.HL)
+        cpu.set_mem8(hl, cpu.get_mem8(hl) | (1 << self.n))
+
+    def pretty(self) -> str:
+        return f"SET {self.n}, (HL)"
+
+
+@dataclass
+class RES_N_R(Insn):
+    n: int
+    r: R8
+
+    def exec(self, cpu: CPU) -> None:
+        cpu.set_reg8(self.r, cpu.get_reg8(self.r) & ~(1 << self.n))
+
+    def pretty(self) -> str:
+        return f"RES {self.n}, (HL)"
+
+
+@dataclass
+class RES_N_HL(Insn):
+    n: int
+
+    def exec(self, cpu: CPU) -> None:
+        hl = cpu.get_reg16(R16.HL)
+        cpu.set_mem8(hl, cpu.get_mem8(hl) & ~(1 << self.n))
+
+    def pretty(self) -> str:
+        return f"RES {self.n}, (HL)"
+
+
+@dataclass
+class CCF(Insn):
+    def exec(self, cpu: CPU) -> None:
+        cpu.carry = cpu.carry ^ 1
+
+    def pretty(self) -> str:
+        return "CCF"
+
+
+@dataclass
+class SCF(Insn):
+    def exec(self, cpu: CPU) -> None:
+        cpu.carry = 1
+
+    def pretty(self) -> str:
+        return "SCF"

gbso/optimize.py

@@ -0,0 +1,5 @@
+from gbso.program import Program
+
+
+def optimize(prgm: Program) -> Program:
+    return prgm

gbso/program.py

@@ -0,0 +1,19 @@
+from dataclasses import dataclass
+from typing import List, Set
+
+from gbso.cpu import CPU
+from gbso.insn import Insn
+from gbso.regs import R8
+
+
+@dataclass
+class Program:
+    outputs: Set[R8]
+    insns: List[Insn]
+
+    # TODO: Memory outputs
+    # TODO: Initialization of registers/memory
+
+    def execute(self, cpu: CPU) -> None:
+        for insn in self.insns:
+            insn.exec(cpu)

gbso/regs.py

@@ -0,0 +1,19 @@
+from enum import Enum
+
+
+class R8(Enum):
+    A = "A"
+    B = "B"
+    C = "C"
+    D = "D"
+    E = "E"
+    H = "H"
+    L = "L"
+
+
+class R16(Enum):
+    AF = "AF"
+    BC = "BC"
+    DE = "DE"
+    HL = "HL"
+    SP = "SP"

poetry.lock

@@ -0,0 +1,231 @@
+[[package]]
+name = "atomicwrites"
+version = "1.4.0"
+description = "Atomic file writes."
+category = "dev"
+optional = false
+python-versions = ">=2.7, !=3.0.*, !=3.1.*, !=3.2.*, !=3.3.*"
+
+[[package]]
+name = "attrs"
+version = "21.2.0"
+description = "Classes Without Boilerplate"
+category = "dev"
+optional = false
+python-versions = ">=2.7, !=3.0.*, !=3.1.*, !=3.2.*, !=3.3.*, !=3.4.*"
+
+[package.extras]
+dev = ["coverage[toml] (>=5.0.2)", "hypothesis", "pympler", "pytest (>=4.3.0)", "six", "mypy", "pytest-mypy-plugins", "zope.interface", "furo", "sphinx", "sphinx-notfound-page", "pre-commit"]
+docs = ["furo", "sphinx", "zope.interface", "sphinx-notfound-page"]
+tests = ["coverage[toml] (>=5.0.2)", "hypothesis", "pympler", "pytest (>=4.3.0)", "six", "mypy", "pytest-mypy-plugins", "zope.interface"]
+tests_no_zope = ["coverage[toml] (>=5.0.2)", "hypothesis", "pympler", "pytest (>=4.3.0)", "six", "mypy", "pytest-mypy-plugins"]
+
+[[package]]
+name = "colorama"
+version = "0.4.4"
+description = "Cross-platform colored terminal text."
+category = "dev"
+optional = false
+python-versions = ">=2.7, !=3.0.*, !=3.1.*, !=3.2.*, !=3.3.*, !=3.4.*"
+
+[[package]]
+name = "more-itertools"
+version = "8.8.0"
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pyproject.toml

@@ -0,0 +1,16 @@
+[tool.poetry]
+name = "gbso"
+version = "0.1.0"
+description = ""
+authors = ["Forest Belton <65484+forestbelton@users.noreply.github.com>"]
+
+[tool.poetry.dependencies]
+python = "^3.9"
+
+[tool.poetry.dev-dependencies]
+pytest = "^5.2"
+mypy = "^0.910"
+
+[build-system]
+requires = ["poetry-core>=1.0.0"]
+build-backend = "poetry.core.masonry.api"

tests/test_gbso.py

@@ -0,0 +1,5 @@
+from gbso import __version__
+
+
+def test_version():
+    assert __version__ == '0.1.0'