diff --git a/gbso/insn.py b/gbso/insn.py
index 3579851..5cb4023 100644
--- a/gbso/insn.py
+++ b/gbso/insn.py
@@ -348,6 +348,9 @@ class AND_A_HL(Insn):
         cpu.set_reg8(R8.A, a)
         cpu.carry = 0
 
+    def pretty(self) -> str:
+        return "AND A, (HL)"
+
 
 @dataclass
 class CP_A_R(Insn):
@@ -356,6 +359,9 @@ class CP_A_R(Insn):
     def exec(self, cpu: CPU) -> None:
         cpu.carry = 1 if cpu.get_reg8(R8.A) < cpu.get_reg8(self.r) else 0
 
+    def pretty(self) -> str:
+        return f"CP A, {self.r.value}"
+
 
 @dataclass
 class CP_A_N(Insn):
@@ -364,12 +370,18 @@ class CP_A_N(Insn):
     def exec(self, cpu: CPU) -> None:
         cpu.carry = 1 if cpu.get_reg8(R8.A) < self.n else 0
 
+    def pretty(self) -> str:
+        return f"CP A, {hex(self.n)}"
+
 
 @dataclass
 class CP_A_HL(Insn):
     def exec(self, cpu: CPU) -> None:
         cpu.carry = 1 if cpu.get_reg8(R8.A) < cpu.get_mem8(cpu.get_reg16(R16.HL)) else 0
 
+    def pretty(self) -> str:
+        return "CP A, (HL)"
+
 
 @dataclass
 class INC_R(Insn):
@@ -378,6 +390,9 @@ class INC_R(Insn):
     def exec(self, cpu: CPU) -> None:
         cpu.set_reg8(self.r, cpu.get_reg8(self.r) + 1)
 
+    def pretty(self) -> str:
+        return f"INC {self.r.value}"
+
 
 @dataclass
 class INC_HL(Insn):
@@ -387,6 +402,9 @@ class INC_HL(Insn):
         hl = cpu.get_reg16(R16.HL)
         cpu.set_mem8(hl, cpu.get_mem8(hl) + 1)
 
+    def pretty(self) -> str:
+        return "INC (HL)"
+
 
 @dataclass
 class DEC_R(Insn):
@@ -395,6 +413,9 @@ class DEC_R(Insn):
     def exec(self, cpu: CPU) -> None:
         cpu.set_reg8(self.r, cpu.get_reg8(self.r) - 1)
 
+    def pretty(self) -> str:
+        return f"DEC {self.r.value}"
+
 
 @dataclass
 class DEC_HL(Insn):
@@ -404,6 +425,9 @@ class DEC_HL(Insn):
         hl = cpu.get_reg16(R16.HL)
         cpu.set_mem8(hl, cpu.get_mem8(hl) - 1)
 
+    def pretty(self) -> str:
+        return "DEC (HL)"
+
 
 @dataclass
 class CPL(Insn):
@@ -420,6 +444,9 @@ class ADD_HL_RR(Insn):
         cpu.carry = 1 if hl > 0xFFFF else 0
         cpu.set_reg16(R16.HL, hl)
 
+    def pretty(self) -> str:
+        return f"ADD HL, {self.rr.value}"
+
 
 @dataclass
 class INC_RR(Insn):
@@ -452,6 +479,9 @@ class ADD_SP_DD(Insn):
         cpu.carry = 1 if sp > 0xFFFF or sp < 0 else 0
         cpu.set_reg16(R16.SP, sp)
 
+    def pretty(self) -> str:
+        return f"ADD SP, {self.dd}"
+
 
 @dataclass
 class LD_HL_SP_DD(Insn):
@@ -462,8 +492,10 @@ class LD_HL_SP_DD(Insn):
         cpu.carry = 1 if sp > 0xFFFF or sp < 0 else 0
         cpu.set_reg16(R16.HL, sp)
 
+    def pretty(self) -> str:
+        return f"LD HL, SP + {self.dd}"
+
 
-# TODO: Rotate and shift instructions
 @dataclass
 class RLCA(Insn):
     def exec(self, cpu: CPU) -> None:
@@ -510,6 +542,9 @@ class RRA(Insn):
         return "RRA"
 
 
+# TODO: Remaining rotate and shift instructions
+
+
 @dataclass
 class SET_N_R(Insn):
     n: int