diff --git a/gbso/cpu.py b/gbso/cpu.py
index 1cef3a3..b63068a 100644
--- a/gbso/cpu.py
+++ b/gbso/cpu.py
@@ -57,8 +57,10 @@ class CPU:
         self.state.memory[nn & 0xFFFF] = (nn1 >> 8) & 0xFF
         self.state.memory[(nn + 1) & 0xFFFF] = nn1 & 0xFF
 
-    def deref_hl(self) -> int:
+    @property
+    def hl(self) -> int:
         return self.get_mem8(self.get_reg16(R16.HL))
 
-    def deref_hl_set(self, n: int) -> None:
+    @hl.setter
+    def hl(self, n: int) -> None:
         self.set_mem8(self.get_reg16(R16.HL), n)
diff --git a/gbso/insn.py b/gbso/insn.py
index 1d1461d..1f4cdad 100644
--- a/gbso/insn.py
+++ b/gbso/insn.py
@@ -58,7 +58,7 @@ class LD_HL_R(Insn):
     src: R8
 
     def exec(self, cpu: CPU) -> None:
-        cpu.deref_hl_set(cpu.get_reg8(self.src))
+        cpu.hl = cpu.get_reg8(self.src)
         cpu.state.cycles += 8
 
     def pretty(self) -> str:
@@ -807,9 +807,8 @@ class RLC_R(Insn):
 @dataclass
 class RLC_HL(Insn):
     def exec(self, cpu: CPU) -> None:
-        hl = cpu.deref_hl()
-        cpu.state.carry = (hl >> 7) & 1
-        cpu.deref_hl_set(((hl << 1) & 0xFF) | cpu.state.carry)
+        cpu.state.carry = (cpu.hl >> 7) & 1
+        cpu.hl = ((cpu.hl << 1) & 0xFF) | cpu.state.carry
         cpu.state.cycles += 16
 
     def pretty(self) -> str:
@@ -834,9 +833,8 @@ class RL_R(Insn):
 @dataclass
 class RL_HL(Insn):
     def exec(self, cpu: CPU) -> None:
-        hl = cpu.deref_hl()
-        next_carry = (hl >> 7) & 1
-        cpu.deref_hl_set(((hl << 1) & 0xFF) | cpu.state.carry)
+        next_carry = (cpu.hl >> 7) & 1
+        cpu.hl = ((cpu.hl << 1) & 0xFF) | cpu.state.carry
         cpu.state.carry = next_carry
         cpu.state.cycles += 16
 
@@ -861,9 +859,8 @@ class RRC_R(Insn):
 @dataclass
 class RRC_HL(Insn):
     def exec(self, cpu: CPU) -> None:
-        hl = cpu.deref_hl()
-        cpu.state.carry = hl & 1
-        cpu.deref_hl_set((hl >> 1) | (cpu.state.carry << 7))
+        cpu.state.carry = cpu.hl & 1
+        cpu.hl = (cpu.hl >> 1) | (cpu.state.carry << 7)
         cpu.state.cycles += 16
 
     def pretty(self) -> str:
@@ -888,9 +885,8 @@ class RR_R(Insn):
 @dataclass
 class RR_HL(Insn):
     def exec(self, cpu: CPU) -> None:
-        hl = cpu.deref_hl()
-        next_carry = hl & 1
-        cpu.deref_hl_set((hl >> 1) | (cpu.state.carry << 7))
+        next_carry = cpu.hl & 1
+        cpu.hl = (cpu.hl >> 1) | (cpu.state.carry << 7)
         cpu.state.carry = next_carry
         cpu.state.cycles += 16
 
@@ -915,9 +911,8 @@ class SLA_R(Insn):
 @dataclass
 class SLA_HL(Insn):
     def exec(self, cpu: CPU) -> None:
-        hl = cpu.deref_hl()
-        cpu.state.carry = 1 if hl & (1 << 7) else 0
-        cpu.deref_hl_set((hl << 1) & 0xFF)
+        cpu.state.carry = 1 if cpu.hl & (1 << 7) else 0
+        cpu.hl = (cpu.hl << 1) & 0xFF
         cpu.state.cycles += 16
 
     def pretty(self) -> str:
@@ -941,8 +936,7 @@ class SWAP_R(Insn):
 @dataclass
 class SWAP_HL(Insn):
     def exec(self, cpu: CPU) -> None:
-        hl = cpu.deref_hl()
-        cpu.deref_hl_set(((hl << 4) & 0xFF) | (hl >> 4))
+        cpu.hl = ((cpu.hl << 4) & 0xFF) | (cpu.hl >> 4)
         cpu.state.carry = 0
         cpu.state.cycles += 16
 
@@ -967,9 +961,8 @@ class SRA_R(Insn):
 @dataclass
 class SRA_HL(Insn):
     def exec(self, cpu: CPU) -> None:
-        hl = cpu.deref_hl()
-        cpu.state.carry = 1 if hl & (1 << 0) else 0
-        cpu.deref_hl_set((hl >> 1) | (hl & (1 << 7)))
+        cpu.state.carry = 1 if cpu.hl & (1 << 0) else 0
+        cpu.hl = (cpu.hl >> 1) | (cpu.hl & (1 << 7))
         cpu.state.cycles += 16
 
     def pretty(self) -> str:
@@ -993,9 +986,8 @@ class SRL_R(Insn):
 @dataclass
 class SRL_HL(Insn):
     def exec(self, cpu: CPU) -> None:
-        hl = cpu.deref_hl()
-        cpu.state.carry = 1 if hl & (1 << 0) else 0
-        cpu.deref_hl_set(hl >> 1)
+        cpu.state.carry = 1 if cpu.hl & (1 << 0) else 0
+        cpu.hl = cpu.hl >> 1
         cpu.state.cycles += 16
 
     def pretty(self) -> str:
diff --git a/tests/insn/test_alu8.py b/tests/insn/test_alu8.py
index 834ee29..717e33e 100644
--- a/tests/insn/test_alu8.py
+++ b/tests/insn/test_alu8.py
@@ -94,7 +94,7 @@ def test_adc_a_n(n):
 def test_adc_a_hl():
     cpu = CPU()
     cpu.set_reg16(R16.HL, 0x1234)
-    cpu.deref_hl_set(0x7F)
+    cpu.hl = 0x7F
 
     ADC_A_HL().exec(cpu)
 
@@ -102,14 +102,14 @@ def test_adc_a_hl():
     assert cpu.state.carry == 0
     assert cpu.state.cycles == 8
 
-    cpu.deref_hl_set(0x81)
+    cpu.hl = 0x81
     ADC_A_HL().exec(cpu)
 
     assert cpu.get_reg8(R8.A) == 0
     assert cpu.state.carry == 1
     assert cpu.state.cycles == 16
 
-    cpu.deref_hl_set(0x00)
+    cpu.hl = 0x00
     ADC_A_HL().exec(cpu)
 
     assert cpu.get_reg8(R8.A) == 1
@@ -310,7 +310,7 @@ def test_inc_hl(n):
 
     INC_HL(n).exec(cpu)
 
-    assert cpu.deref_hl() == (n + 1) & 0xFF
+    assert cpu.hl == (n + 1) & 0xFF
     assert cpu.state.cycles == 12
 
 
@@ -333,7 +333,7 @@ def test_dec_hl(n):
 
     DEC_HL(n).exec(cpu)
 
-    assert cpu.deref_hl() == (n - 1) & 0xFF
+    assert cpu.hl == (n - 1) & 0xFF
     assert cpu.state.cycles == 12
 
 
diff --git a/tests/insn/test_bit.py b/tests/insn/test_bit.py
index 2ac7114..dfc64b0 100644
--- a/tests/insn/test_bit.py
+++ b/tests/insn/test_bit.py
@@ -20,7 +20,7 @@ def test_set_n_hl(n):
 
     SET_N_HL(n).exec(cpu)
 
-    assert cpu.get_mem8(0x1234) == 1 << n
+    assert cpu.hl == 1 << n
     assert cpu.state.cycles == 16
 
 
@@ -43,5 +43,5 @@ def test_res_n_hl(n):
 
     RES_N_HL(n).exec(cpu)
 
-    assert cpu.get_mem8(0x1234) == 0xFF - (1 << n)
+    assert cpu.hl == 0xFF - (1 << n)
     assert cpu.state.cycles == 16
diff --git a/tests/insn/test_loads8.py b/tests/insn/test_loads8.py
index f56fe37..d41991e 100644
--- a/tests/insn/test_loads8.py
+++ b/tests/insn/test_loads8.py
@@ -40,14 +40,13 @@ def test_ld_hl_r(r):
     cpu.set_reg16(R16.HL, 0x1234)
 
     LD_HL_R(r).exec(cpu)
-    hl = cpu.deref_hl()
 
     if r == R8.H:
-        assert hl == 0x12
+        assert cpu.hl == 0x12
     elif r == R8.L:
-        assert hl == 0x34
+        assert cpu.hl == 0x34
     else:
-        assert hl == 0x7F
+        assert cpu.hl == 0x7F
 
     assert cpu.state.cycles == 8
 
@@ -59,7 +58,7 @@ def test_ld_hl_n8(imm):
 
     LD_HL_N(imm).exec(cpu)
 
-    assert cpu.deref_hl() == imm
+    assert cpu.hl == imm
     assert cpu.state.cycles == 12
 
 
diff --git a/tests/insn/test_shift.py b/tests/insn/test_shift.py
index 0635bb5..6361dcf 100644
--- a/tests/insn/test_shift.py
+++ b/tests/insn/test_shift.py
@@ -91,17 +91,17 @@ def test_rlc_r(r):
 
 def test_rlc_hl():
     cpu = CPU()
-    cpu.deref_hl_set(0x80)
+    cpu.hl = 0x80
 
     RLC_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0x01
+    assert cpu.hl == 0x01
     assert cpu.state.carry == 1
     assert cpu.state.cycles == 16
 
     RLC_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0x02
+    assert cpu.hl == 0x02
     assert cpu.state.carry == 0
     assert cpu.state.cycles == 32
 
@@ -126,17 +126,17 @@ def test_rl_r(r):
 
 def test_rl_hl():
     cpu = CPU()
-    cpu.deref_hl_set(0x80)
+    cpu.hl = 0x80
 
     RL_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0x00
+    assert cpu.hl == 0x00
     assert cpu.state.carry == 1
     assert cpu.state.cycles == 16
 
     RL_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0x01
+    assert cpu.hl == 0x01
     assert cpu.state.carry == 0
     assert cpu.state.cycles == 32
 
@@ -162,17 +162,17 @@ def test_rrc_r(r):
 def test_rrc_hl():
     cpu = CPU()
     cpu.set_reg16(R16.HL, 0x1234)
-    cpu.deref_hl_set(0x01)
+    cpu.hl = 0x01
 
     RRC_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0x80
+    assert cpu.hl == 0x80
     assert cpu.state.carry == 1
     assert cpu.state.cycles == 16
 
     RRC_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0x40
+    assert cpu.hl == 0x40
     assert cpu.state.carry == 0
     assert cpu.state.cycles == 32
 
@@ -198,17 +198,17 @@ def test_rr_r(r):
 def test_rr_hl():
     cpu = CPU()
     cpu.set_reg16(R16.HL, 0x1234)
-    cpu.deref_hl_set(0x01)
+    cpu.hl = 0x01
 
     RR_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0x00
+    assert cpu.hl == 0x00
     assert cpu.state.carry == 1
     assert cpu.state.cycles == 16
 
     RR_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0x80
+    assert cpu.hl == 0x80
     assert cpu.state.carry == 0
     assert cpu.state.cycles == 32
 
@@ -235,18 +235,18 @@ def test_sla_r(r):
 def test_sla_hl():
     cpu = CPU()
     cpu.set_reg16(R16.HL, 0x1234)
-    cpu.deref_hl_set(0xFF)
+    cpu.hl = 0xFF
 
     SLA_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0xFE
+    assert cpu.hl == 0xFE
     assert cpu.state.carry == 1
     assert cpu.state.cycles == 16
 
-    cpu.deref_hl_set(0x01)
+    cpu.hl = 0x01
     SLA_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0x02
+    assert cpu.hl == 0x02
     assert cpu.state.carry == 0
     assert cpu.state.cycles == 32
 
@@ -266,11 +266,11 @@ def test_swap_r(r):
 def test_swap_hl():
     cpu = CPU()
     cpu.set_reg16(R16.HL, 0x1234)
-    cpu.deref_hl_set(0xAB)
+    cpu.hl = 0xAB
 
     SWAP_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0xBA
+    assert cpu.hl == 0xBA
     assert cpu.state.carry == 0
     assert cpu.state.cycles == 16
 
@@ -297,18 +297,18 @@ def test_sra_r(r):
 def test_sra_hl():
     cpu = CPU()
     cpu.set_reg16(R16.HL, 0x1234)
-    cpu.deref_hl_set(0xFF)
+    cpu.hl = 0xFF
 
     SRA_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0xFF
+    assert cpu.hl == 0xFF
     assert cpu.state.carry == 1
     assert cpu.state.cycles == 16
 
-    cpu.deref_hl_set(0x02)
+    cpu.hl = 0x02
     SRA_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0x01
+    assert cpu.hl == 0x01
     assert cpu.state.carry == 0
     assert cpu.state.cycles == 32
 
@@ -335,17 +335,17 @@ def test_srl_r(r):
 def test_srl_hl():
     cpu = CPU()
     cpu.set_reg16(R16.HL, 0x1234)
-    cpu.deref_hl_set(0xFF)
+    cpu.hl = 0xFF
 
     SRL_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0x7F
+    assert cpu.hl == 0x7F
     assert cpu.state.carry == 1
     assert cpu.state.cycles == 16
 
-    cpu.deref_hl_set(0x02)
+    cpu.hl = 0x02
     SRL_HL().exec(cpu)
 
-    assert cpu.deref_hl() == 0x01
+    assert cpu.hl == 0x01
     assert cpu.state.carry == 0
     assert cpu.state.cycles == 32
diff --git a/tests/test_gbso.py b/tests/test_gbso.py
deleted file mode 100644
index a32ff18..0000000
--- a/tests/test_gbso.py
+++ /dev/null
@@ -1,5 +0,0 @@
-from gbso import __version__
-
-
-def test_version():
-    assert __version__ == '0.1.0'