diff --git a/gbso/insn.py b/gbso/insn.py
index 31e75c4..ccee90a 100644
--- a/gbso/insn.py
+++ b/gbso/insn.py
@@ -680,6 +680,7 @@ class ADD_HL_RR(Insn):
         hl = cpu.get_reg16(R16.HL) + cpu.get_reg16(self.rr)
         cpu.carry = 1 if hl > 0xFFFF else 0
         cpu.set_reg16(R16.HL, hl)
+        cpu.cycles += 8
 
     def pretty(self) -> str:
         return f"ADD HL, {self.rr.value}"
@@ -691,6 +692,7 @@ class INC_RR(Insn):
 
     def exec(self, cpu: CPU) -> None:
         cpu.set_reg16(self.rr, cpu.get_reg16(self.rr) + 1)
+        cpu.cycles += 8
 
     def pretty(self) -> str:
         return f"INC {self.rr.value}"
@@ -702,6 +704,7 @@ class DEC_RR(Insn):
 
     def exec(self, cpu: CPU) -> None:
         cpu.set_reg16(self.rr, cpu.get_reg16(self.rr) - 1)
+        cpu.cycles += 8
 
     def pretty(self) -> str:
         return f"DEC {self.rr.value}"
diff --git a/tests/insn/test_alu16.py b/tests/insn/test_alu16.py
new file mode 100644
index 0000000..05c4963
--- /dev/null
+++ b/tests/insn/test_alu16.py
@@ -0,0 +1,45 @@
+import pytest
+
+from tests.insn.helpers import *
+
+
+@pytest.mark.parametrize("rr", set(R16) - {R16.AF, R16.HL})
+def test_add_hl_rr(rr):
+    cpu = CPU()
+    cpu.set_reg16(R16.HL, 0xABCD)
+    cpu.set_reg16(rr, 0x1234)
+
+    ADD_HL_RR(rr).exec(cpu)
+
+    assert cpu.get_reg16(R16.HL) == 0xBE01
+    assert cpu.carry == 0
+    assert cpu.cycles == 8
+
+    cpu.set_reg16(rr, 0xFFFF - 0xBE01 + 1)
+    ADD_HL_RR(rr).exec(cpu)
+
+    assert cpu.get_reg16(R16.HL) == 0
+    assert cpu.carry == 1
+    assert cpu.cycles == 16
+
+
+@pytest.mark.parametrize("rr", set(R16) - {R16.AF})
+def test_inc_rr(rr):
+    cpu = CPU()
+    cpu.set_reg16(rr, 0xABCD)
+
+    INC_RR(rr).exec(cpu)
+
+    assert cpu.get_reg16(rr) == 0xABCE
+    assert cpu.cycles == 8
+
+
+@pytest.mark.parametrize("rr", set(R16) - {R16.AF})
+def test_dec_rr(rr):
+    cpu = CPU()
+    cpu.set_reg16(rr, 0xABCD)
+
+    DEC_RR(rr).exec(cpu)
+
+    assert cpu.get_reg16(rr) == 0xABCC
+    assert cpu.cycles == 8