|
|
@ -1,17 +1,7 @@ |
|
|
|
from collections import defaultdict |
|
|
|
from dataclasses import dataclass, field |
|
|
|
from typing import Dict, Optional |
|
|
|
from typing import Optional |
|
|
|
|
|
|
|
from gbso.regs import R16_HI, R16_LO, R8, R16 |
|
|
|
|
|
|
|
|
|
|
|
@dataclass |
|
|
|
class CPUState: |
|
|
|
carry: int = 0 |
|
|
|
cycles: int = 0 |
|
|
|
sp: int = 0 |
|
|
|
reg8: Dict[R8, int] = field(default_factory=lambda: defaultdict(lambda: 0)) |
|
|
|
memory: Dict[int, int] = field(default_factory=lambda: defaultdict(lambda: 0)) |
|
|
|
from gbso.cpu.regs import R16_HI, R16_LO, R8, R16 |
|
|
|
from gbso.cpu.state import CPUState |
|
|
|
|
|
|
|
|
|
|
|
class CPU: |
|
|
@ -46,9 +36,9 @@ class CPU: |
|
|
|
return self.state.memory[nn & 0xFFFF] |
|
|
|
|
|
|
|
def get_mem16(self, nn: int) -> int: |
|
|
|
return (self.state.memory[nn & 0xFFFF] << 8) | self.state.memory[ |
|
|
|
(nn + 1) & 0xFFFF |
|
|
|
] |
|
|
|
hi = self.state.memory[nn & 0xFFFF] |
|
|
|
lo = self.state.memory[(nn + 1) & 0xFFFF] |
|
|
|
return (hi << 8) | lo |
|
|
|
|
|
|
|
def set_mem8(self, nn: int, n: int) -> None: |
|
|
|
self.state.memory[nn & 0xFFFF] = n & 0xFF |