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869 lines
18 KiB
869 lines
18 KiB
from abc import ABC, abstractmethod
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from dataclasses import dataclass
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from gbso.cpu import CPU
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from gbso.regs import R16, R8
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class Insn(ABC):
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@abstractmethod
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def exec(self, cpu: CPU) -> None:
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pass
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# TODO: Make abstract once all subclasses implement
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def pretty(self) -> str:
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return ""
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@dataclass
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class LD_R_R(Insn):
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dst: R8
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src: R8
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg8(self.dst, cpu.get_reg8(self.src))
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cpu.cycles += 4
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def pretty(self) -> str:
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return f"LD {self.dst}, {self.src}"
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@dataclass
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class LD_R_N8(Insn):
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dst: R8
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imm: int
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg8(self.dst, self.imm)
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cpu.cycles += 8
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def pretty(self) -> str:
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return f"LD {self.dst}, {hex(self.imm)}"
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@dataclass
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class LD_R_HL(Insn):
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dst: R8
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg8(self.dst, cpu.get_mem8(cpu.get_reg16(R16.HL)))
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cpu.cycles += 8
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def pretty(self) -> str:
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return f"LD {self.dst}, (HL)"
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@dataclass
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class LD_HL_R(Insn):
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src: R8
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def exec(self, cpu: CPU) -> None:
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cpu.deref_hl_set(cpu.get_reg8(self.src))
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cpu.cycles += 8
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def pretty(self) -> str:
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return f"LD (HL), {self.src}"
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@dataclass
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class LD_HL_N(Insn):
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imm: int
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def exec(self, cpu: CPU) -> None:
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cpu.set_mem8(cpu.get_reg16(R16.HL), self.imm)
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cpu.cycles += 12
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def pretty(self) -> str:
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return f"LD (HL), {hex(self.imm & 0xff)}"
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@dataclass
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class LD_A_BC(Insn):
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg8(R8.A, cpu.get_mem8(cpu.get_reg16(R16.BC)))
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cpu.cycles += 8
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def pretty(self) -> str:
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return "LD A, (BC)"
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@dataclass
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class LD_A_DE(Insn):
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg8(R8.A, cpu.get_mem8(cpu.get_reg16(R16.DE)))
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cpu.cycles += 8
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def pretty(self) -> str:
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return "LD A, (DE)"
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@dataclass
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class LD_A_NN(Insn):
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nn: int
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg8(R8.A, cpu.get_mem8(self.nn))
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cpu.cycles += 16
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def pretty(self) -> str:
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return f"LD A, ({hex(self.nn)})"
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@dataclass
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class LD_BC_A(Insn):
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def exec(self, cpu: CPU) -> None:
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cpu.set_mem8(cpu.get_reg16(R16.BC), cpu.get_reg8(R8.A))
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cpu.cycles += 8
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def pretty(self) -> str:
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return "LD (BC), A"
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@dataclass
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class LD_DE_A(Insn):
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def exec(self, cpu: CPU) -> None:
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cpu.set_mem8(cpu.get_reg16(R16.DE), cpu.get_reg8(R8.A))
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cpu.cycles += 8
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def pretty(self) -> str:
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return "LD (DE), A"
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@dataclass
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class LD_NN_A(Insn):
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nn: int
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def exec(self, cpu: CPU) -> None:
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cpu.set_mem8(self.nn, cpu.get_reg8(R8.A))
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cpu.cycles += 16
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def pretty(self) -> str:
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return f"LD ({hex(self.nn)}), A"
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@dataclass
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class LD_A_FF_N(Insn):
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n: int
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg8(R8.A, cpu.get_mem8(0xFF00 + self.n))
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cpu.cycles += 12
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def pretty(self) -> str:
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return f"LD A, (0xFF00 + {hex(self.n)})"
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@dataclass
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class LD_FF_N_A(Insn):
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n: int
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def exec(self, cpu: CPU) -> None:
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cpu.set_mem8(0xFF00 + self.n, cpu.get_reg8(R8.A))
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cpu.cycles += 12
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def pretty(self) -> str:
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return f"LD (0xFF00 + {hex(self.n)}), A"
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@dataclass
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class LD_A_FF_C(Insn):
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg8(R8.A, cpu.get_mem8(0xFF00 + cpu.get_reg8(R8.C)))
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cpu.cycles += 8
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def pretty(self) -> str:
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return "LD A, (0xFF00 + C)"
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@dataclass
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class LD_FF_C_A(Insn):
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def exec(self, cpu: CPU) -> None:
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cpu.set_mem8(0xFF00 + cpu.get_reg8(R8.C), cpu.get_reg8(R8.A))
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cpu.cycles += 8
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def pretty(self) -> str:
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return "LD (0xFF00 + C), A"
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@dataclass
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class LDI_HL_A(Insn):
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def exec(self, cpu: CPU) -> None:
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hl = cpu.get_reg16(R16.HL)
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cpu.set_mem8(hl, cpu.get_reg8(R8.A))
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cpu.set_reg16(R16.HL, hl + 1)
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cpu.cycles += 8
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def pretty(self) -> str:
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return "LDI (HL), A"
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@dataclass
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class LDI_A_HL(Insn):
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def exec(self, cpu: CPU) -> None:
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hl = cpu.get_reg16(R16.HL)
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cpu.set_reg8(R8.A, cpu.get_mem8(hl))
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cpu.set_reg16(R16.HL, hl + 1)
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cpu.cycles += 8
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def pretty(self) -> str:
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return "LDI A, (HL)"
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@dataclass
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class LDD_HL_A(Insn):
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def exec(self, cpu: CPU) -> None:
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hl = cpu.get_reg16(R16.HL)
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cpu.set_mem8(hl, cpu.get_reg8(R8.A))
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cpu.set_reg16(R16.HL, hl - 1)
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cpu.cycles += 8
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def pretty(self) -> str:
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return "LDD (HL), A"
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@dataclass
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class LDD_A_HL(Insn):
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def exec(self, cpu: CPU) -> None:
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hl = cpu.get_reg16(R16.HL)
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cpu.set_reg8(R8.A, cpu.get_mem8(hl))
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cpu.set_reg16(R16.HL, hl - 1)
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cpu.cycles += 8
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def pretty(self) -> str:
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return "LDD A, (HL)"
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@dataclass
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class LD_RR_NN(Insn):
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rr: R16
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nn: int
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg16(self.rr, self.nn)
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def pretty(self) -> str:
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return f"LD {self.rr.value}, {hex(self.nn)}"
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@dataclass
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class LD_NN_SP(Insn):
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nn: int
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def exec(self, cpu: CPU) -> None:
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cpu.set_mem16(self.nn, cpu.get_reg16(R16.SP))
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@dataclass
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class LD_SP_HL(Insn):
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg16(R16.SP, cpu.get_reg16(R16.HL))
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@dataclass
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class PUSH_RR(Insn):
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rr: R16
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def exec(self, cpu: CPU) -> None:
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sp = cpu.get_reg16(R16.SP)
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cpu.set_reg16(R16.SP, sp - 2)
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cpu.set_mem16(sp - 2, cpu.get_reg16(self.rr))
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@dataclass
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class POP_RR(Insn):
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rr: R16
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def exec(self, cpu: CPU) -> None:
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sp = cpu.get_reg16(R16.SP)
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cpu.set_reg16(self.rr, cpu.get_mem16(sp))
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cpu.set_reg16(R16.SP, sp + 2)
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@dataclass
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class ADD_A_R(Insn):
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r: R8
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) + cpu.get_reg8(self.r)
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cpu.carry = 1 if a > 0xFF else 0
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cpu.set_reg8(R8.A, a)
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@dataclass
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class ADD_A_N(Insn):
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n: int
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) + self.n
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cpu.carry = 1 if a > 0xFF else 0
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cpu.set_reg8(R8.A, a)
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@dataclass
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class ADD_A_HL(Insn):
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) + cpu.get_mem8(cpu.get_reg16(R16.HL))
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cpu.carry = 1 if a > 0xFF else 0
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cpu.set_reg8(R8.A, a)
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@dataclass
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class ADC_A_R(Insn):
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r: R8
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) + cpu.get_reg8(self.r) + cpu.carry
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cpu.carry = 1 if a > 0xFF else 0
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cpu.set_reg8(R8.A, a)
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@dataclass
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class ADC_A_N(Insn):
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n: int
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) + self.n + cpu.carry
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cpu.carry = 1 if a > 0xFF else 0
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cpu.set_reg8(R8.A, a)
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@dataclass
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class ADC_A_HL(Insn):
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) + cpu.get_mem8(cpu.get_reg16(R16.HL)) + cpu.carry
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cpu.carry = 1 if a > 0xFF else 0
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cpu.set_reg8(R8.A, a)
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@dataclass
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class SUB_A_R(Insn):
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r: R8
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) - cpu.get_reg8(self.r)
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cpu.carry = 1 if a < 0 else 0
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cpu.set_reg8(R8.A, a)
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@dataclass
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class SUB_A_N(Insn):
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n: int
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) - self.n
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cpu.carry = 1 if a < 0 else 0
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cpu.set_reg8(R8.A, a)
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@dataclass
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class SUB_A_HL(Insn):
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) - cpu.get_mem8(cpu.get_reg16(R16.HL))
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cpu.carry = 1 if a < 0 else 0
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cpu.set_reg8(R8.A, a)
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@dataclass
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class SBC_A_R(Insn):
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r: R8
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) - cpu.get_reg8(self.r) - cpu.carry
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cpu.carry = 1 if a < 0 else 0
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cpu.set_reg8(R8.A, a)
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@dataclass
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class SBC_A_N(Insn):
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n: int
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) - self.n - cpu.carry
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cpu.carry = 1 if a < 0 else 0
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cpu.set_reg8(R8.A, a)
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@dataclass
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class SBC_A_HL(Insn):
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) - cpu.get_mem8(cpu.get_reg16(R16.HL)) - cpu.carry
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cpu.carry = 1 if a < 0 else 0
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cpu.set_reg8(R8.A, a)
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@dataclass
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class AND_A_R(Insn):
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r: R8
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) & cpu.get_reg8(self.r)
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cpu.set_reg8(R8.A, a)
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cpu.carry = 0
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@dataclass
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class AND_A_N(Insn):
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n: int
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) & self.n
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cpu.set_reg8(R8.A, a)
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cpu.carry = 0
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@dataclass
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class AND_A_HL(Insn):
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def exec(self, cpu: CPU) -> None:
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a = cpu.get_reg8(R8.A) & cpu.get_mem8(cpu.get_reg16(R16.HL))
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cpu.set_reg8(R8.A, a)
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cpu.carry = 0
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def pretty(self) -> str:
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return "AND A, (HL)"
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@dataclass
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class CP_A_R(Insn):
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r: R8
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def exec(self, cpu: CPU) -> None:
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cpu.carry = 1 if cpu.get_reg8(R8.A) < cpu.get_reg8(self.r) else 0
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def pretty(self) -> str:
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return f"CP A, {self.r.value}"
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@dataclass
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class CP_A_N(Insn):
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n: int
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def exec(self, cpu: CPU) -> None:
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cpu.carry = 1 if cpu.get_reg8(R8.A) < self.n else 0
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def pretty(self) -> str:
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return f"CP A, {hex(self.n)}"
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@dataclass
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class CP_A_HL(Insn):
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def exec(self, cpu: CPU) -> None:
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cpu.carry = 1 if cpu.get_reg8(R8.A) < cpu.get_mem8(cpu.get_reg16(R16.HL)) else 0
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def pretty(self) -> str:
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return "CP A, (HL)"
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@dataclass
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class INC_R(Insn):
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r: R8
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg8(self.r, cpu.get_reg8(self.r) + 1)
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def pretty(self) -> str:
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return f"INC {self.r.value}"
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@dataclass
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class INC_HL(Insn):
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r: R8
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def exec(self, cpu: CPU) -> None:
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hl = cpu.get_reg16(R16.HL)
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cpu.set_mem8(hl, cpu.get_mem8(hl) + 1)
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def pretty(self) -> str:
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return "INC (HL)"
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@dataclass
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class DEC_R(Insn):
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r: R8
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg8(self.r, cpu.get_reg8(self.r) - 1)
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def pretty(self) -> str:
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return f"DEC {self.r.value}"
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@dataclass
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class DEC_HL(Insn):
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r: R8
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def exec(self, cpu: CPU) -> None:
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hl = cpu.get_reg16(R16.HL)
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cpu.set_mem8(hl, cpu.get_mem8(hl) - 1)
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def pretty(self) -> str:
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return "DEC (HL)"
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@dataclass
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class CPL(Insn):
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg8(R8.A, cpu.get_reg8(R8.A) ^ 0xFF)
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@dataclass
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class ADD_HL_RR(Insn):
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rr: R16
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def exec(self, cpu: CPU) -> None:
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hl = cpu.get_reg16(R16.HL) + cpu.get_reg16(self.rr)
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cpu.carry = 1 if hl > 0xFFFF else 0
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cpu.set_reg16(R16.HL, hl)
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def pretty(self) -> str:
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return f"ADD HL, {self.rr.value}"
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@dataclass
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class INC_RR(Insn):
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rr: R16
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg16(self.rr, cpu.get_reg16(self.rr) + 1)
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def pretty(self) -> str:
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return f"INC {self.rr.value}"
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@dataclass
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class DEC_RR(Insn):
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rr: R16
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def exec(self, cpu: CPU) -> None:
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cpu.set_reg16(self.rr, cpu.get_reg16(self.rr) - 1)
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def pretty(self) -> str:
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return f"DEC {self.rr.value}"
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@dataclass
|
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class ADD_SP_DD(Insn):
|
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dd: int
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def exec(self, cpu: CPU) -> None:
|
|
sp = cpu.get_reg16(R16.SP) + self.dd
|
|
cpu.carry = 1 if sp > 0xFFFF or sp < 0 else 0
|
|
cpu.set_reg16(R16.SP, sp)
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|
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|
def pretty(self) -> str:
|
|
return f"ADD SP, {self.dd}"
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@dataclass
|
|
class LD_HL_SP_DD(Insn):
|
|
dd: int
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|
|
|
def exec(self, cpu: CPU) -> None:
|
|
sp = cpu.get_reg16(R16.SP) + self.dd
|
|
cpu.carry = 1 if sp > 0xFFFF or sp < 0 else 0
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|
cpu.set_reg16(R16.HL, sp)
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|
|
|
def pretty(self) -> str:
|
|
return f"LD HL, SP + {self.dd}"
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|
|
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|
|
@dataclass
|
|
class RLCA(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
a = cpu.get_reg8(R8.A)
|
|
cpu.carry = (a >> 7) & 1
|
|
cpu.set_reg8(R8.A, ((a << 1) & 0xFF) | cpu.carry)
|
|
|
|
def pretty(self) -> str:
|
|
return "RLCA"
|
|
|
|
|
|
@dataclass
|
|
class RLA(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
a = cpu.get_reg8(R8.A)
|
|
next_carry = (a >> 7) & 1
|
|
cpu.set_reg8(R8.A, ((a << 1) & 0xFF) | cpu.carry)
|
|
cpu.carry = next_carry
|
|
|
|
def pretty(self) -> str:
|
|
return "RLA"
|
|
|
|
|
|
@dataclass
|
|
class RRCA(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
a = cpu.get_reg8(R8.A)
|
|
cpu.carry = a & 1
|
|
cpu.set_reg8(R8.A, (a >> 1) | (cpu.carry << 7))
|
|
|
|
def pretty(self) -> str:
|
|
return "RRCA"
|
|
|
|
|
|
@dataclass
|
|
class RRA(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
a = cpu.get_reg8(R8.A)
|
|
next_carry = a & 1
|
|
cpu.set_reg8(R8.A, (a >> 1) | (cpu.carry << 7))
|
|
cpu.carry = next_carry
|
|
|
|
def pretty(self) -> str:
|
|
return "RRA"
|
|
|
|
|
|
@dataclass
|
|
class RLC_R(Insn):
|
|
r: R8
|
|
|
|
def exec(self, cpu: CPU) -> None:
|
|
r = cpu.get_reg8(self.r)
|
|
cpu.carry = (r >> 7) & 1
|
|
cpu.set_reg8(self.r, ((r << 1) & 0xFF) | cpu.carry)
|
|
|
|
def pretty(self) -> str:
|
|
return f"RLC {self.r}"
|
|
|
|
|
|
@dataclass
|
|
class RLC_HL(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
hl = cpu.deref_hl()
|
|
cpu.carry = (hl >> 7) & 1
|
|
cpu.deref_hl_set(((hl << 1) & 0xFF) | cpu.carry)
|
|
|
|
def pretty(self) -> str:
|
|
return f"RLC (HL)"
|
|
|
|
|
|
@dataclass
|
|
class RL_R(Insn):
|
|
r: R8
|
|
|
|
def exec(self, cpu: CPU) -> None:
|
|
r = cpu.get_reg8(self.r)
|
|
next_carry = (r >> 7) & 1
|
|
cpu.set_reg8(self.r, ((r << 1) & 0xFF) | cpu.carry)
|
|
cpu.carry = next_carry
|
|
|
|
def pretty(self) -> str:
|
|
return f"RL {self.r}"
|
|
|
|
|
|
@dataclass
|
|
class RL_HL(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
hl = cpu.deref_hl()
|
|
next_carry = (hl >> 7) & 1
|
|
cpu.deref_hl_set(((hl << 1) & 0xFF) | cpu.carry)
|
|
cpu.carry = next_carry
|
|
|
|
def pretty(self) -> str:
|
|
return "RL (HL)"
|
|
|
|
|
|
@dataclass
|
|
class RRC_R(Insn):
|
|
r: R8
|
|
|
|
def exec(self, cpu: CPU) -> None:
|
|
r = cpu.get_reg8(self.r)
|
|
cpu.carry = r & 1
|
|
cpu.set_reg8(self.r, (r >> 1) | (cpu.carry << 7))
|
|
|
|
def pretty(self) -> str:
|
|
return f"RRC {self.r}"
|
|
|
|
|
|
@dataclass
|
|
class RRC_HL(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
hl = cpu.deref_hl()
|
|
cpu.carry = hl & 1
|
|
cpu.deref_hl_set((hl >> 1) | (cpu.carry << 7))
|
|
|
|
def pretty(self) -> str:
|
|
return "RRC (HL)"
|
|
|
|
|
|
@dataclass
|
|
class RR_R(Insn):
|
|
r: R8
|
|
|
|
def exec(self, cpu: CPU) -> None:
|
|
r = cpu.get_reg8(self.r)
|
|
next_carry = r & 1
|
|
cpu.set_reg8(self.r, (r >> 1) | (cpu.carry << 7))
|
|
cpu.carry = next_carry
|
|
|
|
def pretty(self) -> str:
|
|
return f"RR {self.r}"
|
|
|
|
|
|
@dataclass
|
|
class RR_HL(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
hl = cpu.deref_hl()
|
|
next_carry = hl & 1
|
|
cpu.deref_hl_set((hl >> 1) | (cpu.carry << 7))
|
|
cpu.carry = next_carry
|
|
|
|
def pretty(self) -> str:
|
|
return "RR (HL)"
|
|
|
|
|
|
@dataclass
|
|
class SLA_R(Insn):
|
|
r: R8
|
|
|
|
def exec(self, cpu: CPU) -> None:
|
|
r = cpu.get_reg8(self.r)
|
|
cpu.set_reg8(self.r, (r << 1) & 0xFF)
|
|
|
|
def pretty(self) -> str:
|
|
return f"SLA {self.r}"
|
|
|
|
|
|
@dataclass
|
|
class SLA_HL(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
hl = cpu.deref_hl()
|
|
cpu.deref_hl_set((hl << 1) & 0xFF)
|
|
|
|
def pretty(self) -> str:
|
|
return "SLA (HL)"
|
|
|
|
|
|
@dataclass
|
|
class SWAP_R(Insn):
|
|
r: R8
|
|
|
|
def exec(self, cpu: CPU) -> None:
|
|
r = cpu.get_reg8(self.r)
|
|
cpu.set_reg8(self.r, ((r << 4) & 0xFF) | (r >> 4))
|
|
|
|
def pretty(self) -> str:
|
|
return f"SWAP {self.r}"
|
|
|
|
|
|
@dataclass
|
|
class SWAP_HL(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
hl = cpu.deref_hl()
|
|
cpu.deref_hl_set(((hl << 4) & 0xFF) | (hl >> 4))
|
|
|
|
def pretty(self) -> str:
|
|
return "SWAP (HL)"
|
|
|
|
|
|
@dataclass
|
|
class SRA_R(Insn):
|
|
r: R8
|
|
|
|
def exec(self, cpu: CPU) -> None:
|
|
r = cpu.get_reg8(self.r)
|
|
cpu.set_reg8(self.r, (r >> 1) | (r & (1 << 7)))
|
|
|
|
def pretty(self) -> str:
|
|
return f"SRA {self.r}"
|
|
|
|
|
|
@dataclass
|
|
class SRA_HL(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
hl = cpu.deref_hl()
|
|
cpu.deref_hl_set((hl >> 1) | (hl & (1 << 7)))
|
|
|
|
def pretty(self) -> str:
|
|
return "SRA (HL)"
|
|
|
|
|
|
@dataclass
|
|
class SRL_R(Insn):
|
|
r: R8
|
|
|
|
def exec(self, cpu: CPU) -> None:
|
|
r = cpu.get_reg8(self.r)
|
|
cpu.set_reg8(self.r, r >> 1)
|
|
|
|
def pretty(self) -> str:
|
|
return f"SRL {self.r}"
|
|
|
|
|
|
@dataclass
|
|
class SRL_HL(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
hl = cpu.deref_hl()
|
|
cpu.deref_hl_set(hl >> 1)
|
|
|
|
def pretty(self) -> str:
|
|
return "SRL (HL)"
|
|
|
|
|
|
# TODO: Remaining rotate and shift instructions
|
|
|
|
|
|
@dataclass
|
|
class SET_N_R(Insn):
|
|
n: int
|
|
r: R8
|
|
|
|
def exec(self, cpu: CPU) -> None:
|
|
cpu.set_reg8(self.r, cpu.get_reg8(self.r) | (1 << self.n))
|
|
|
|
def pretty(self) -> str:
|
|
return f"SET {self.n}, (HL)"
|
|
|
|
|
|
@dataclass
|
|
class SET_N_HL(Insn):
|
|
n: int
|
|
|
|
def exec(self, cpu: CPU) -> None:
|
|
hl = cpu.get_reg16(R16.HL)
|
|
cpu.set_mem8(hl, cpu.get_mem8(hl) | (1 << self.n))
|
|
|
|
def pretty(self) -> str:
|
|
return f"SET {self.n}, (HL)"
|
|
|
|
|
|
@dataclass
|
|
class RES_N_R(Insn):
|
|
n: int
|
|
r: R8
|
|
|
|
def exec(self, cpu: CPU) -> None:
|
|
cpu.set_reg8(self.r, cpu.get_reg8(self.r) & ~(1 << self.n))
|
|
|
|
def pretty(self) -> str:
|
|
return f"RES {self.n}, (HL)"
|
|
|
|
|
|
@dataclass
|
|
class RES_N_HL(Insn):
|
|
n: int
|
|
|
|
def exec(self, cpu: CPU) -> None:
|
|
hl = cpu.get_reg16(R16.HL)
|
|
cpu.set_mem8(hl, cpu.get_mem8(hl) & ~(1 << self.n))
|
|
|
|
def pretty(self) -> str:
|
|
return f"RES {self.n}, (HL)"
|
|
|
|
|
|
@dataclass
|
|
class CCF(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
cpu.carry = cpu.carry ^ 1
|
|
|
|
def pretty(self) -> str:
|
|
return "CCF"
|
|
|
|
|
|
@dataclass
|
|
class SCF(Insn):
|
|
def exec(self, cpu: CPU) -> None:
|
|
cpu.carry = 1
|
|
|
|
def pretty(self) -> str:
|
|
return "SCF"
|