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  1. ;*
  2. ;* Gameboy Hardware definitions
  3. ;*
  4. ;* Based on Jones' hardware.inc
  5. ;* And based on Carsten Sorensen's ideas.
  6. ;*
  7. ;* Rev 1.1 - 15-Jul-97 : Added define check
  8. ;* Rev 1.2 - 18-Jul-97 : Added revision check macro
  9. ;* Rev 1.3 - 19-Jul-97 : Modified for RGBASM V1.05
  10. ;* Rev 1.4 - 27-Jul-97 : Modified for new subroutine prefixes
  11. ;* Rev 1.5 - 15-Aug-97 : Added _HRAM, PAD, CART defines
  12. ;* : and Nintendo Logo
  13. ;* Rev 1.6 - 30-Nov-97 : Added rDIV, rTIMA, rTMA, & rTAC
  14. ;* Rev 1.7 - 31-Jan-98 : Added _SCRN0, _SCRN1
  15. ;* Rev 1.8 - 15-Feb-98 : Added rSB, rSC
  16. ;* Rev 1.9 - 16-Feb-98 : Converted I/O registers to $FFXX format
  17. ;* Rev 2.0 - : Added GBC registers
  18. ;* Rev 2.1 - : Added MBC5 & cart RAM enable/disable defines
  19. ;* Rev 2.2 - : Fixed NR42,NR43, & NR44 equates
  20. ;* Rev 2.3 - : Fixed incorrect _HRAM equate
  21. ;* Rev 2.4 - 27-Apr-13 : Added some cart defines (AntonioND)
  22. ;* Rev 2.5 - 03-May-15 : Fixed format (AntonioND)
  23. ;* Rev 2.6 - 09-Apr-16 : Added GBC OAM and cart defines (AntonioND)
  24. ;* Rev 2.7 - 19-Jan-19 : Added rPCMXX (ISSOtm)
  25. ;* Rev 2.8 - 03-Feb-19 : Added audio registers flags (lvaro Cuesta)
  26. ;* Rev 2.9 - 28-Feb-20 : Added utility rP1 constants
  27. ;* Rev 3.0 - 27-Aug-20 : Register ordering, byte-based sizes, OAM additions, general cleanup (Blitter Object)
  28. ; If all of these are already defined, don't do it again.
  29. IF !DEF(HARDWARE_INC)
  30. HARDWARE_INC SET 1
  31. rev_Check_hardware_inc : MACRO
  32. ;NOTE: REVISION NUMBER CHANGES MUST BE ADDED
  33. ;TO SECOND PARAMETER IN FOLLOWING LINE.
  34. IF \1 > 3.0 ;PUT REVISION NUMBER HERE
  35. WARN "Version \1 or later of 'hardware.inc' is required."
  36. ENDC
  37. ENDM
  38. _VRAM EQU $8000 ; $8000->$9FFF
  39. _VRAM8000 EQU _VRAM
  40. _VRAM8800 EQU _VRAM+$800
  41. _VRAM9000 EQU _VRAM+$1000
  42. _SCRN0 EQU $9800 ; $9800->$9BFF
  43. _SCRN1 EQU $9C00 ; $9C00->$9FFF
  44. _SRAM EQU $A000 ; $A000->$BFFF
  45. _RAM EQU $C000 ; $C000->$CFFF / $C000->$DFFF
  46. _RAMBANK EQU $D000 ; $D000->$DFFF
  47. _OAMRAM EQU $FE00 ; $FE00->$FE9F
  48. _IO EQU $FF00 ; $FF00->$FF7F,$FFFF
  49. _AUD3WAVERAM EQU $FF30 ; $FF30->$FF3F
  50. _HRAM EQU $FF80 ; $FF80->$FFFE
  51. ; *** MBC5 Equates ***
  52. rRAMG EQU $0000 ; $0000->$1fff
  53. rROMB0 EQU $2000 ; $2000->$2fff
  54. rROMB1 EQU $3000 ; $3000->$3fff - If more than 256 ROM banks are present.
  55. rRAMB EQU $4000 ; $4000->$5fff - Bit 3 enables rumble (if present)
  56. ;***************************************************************************
  57. ;*
  58. ;* Custom registers
  59. ;*
  60. ;***************************************************************************
  61. ; --
  62. ; -- P1 ($FF00)
  63. ; -- Register for reading joy pad info. (R/W)
  64. ; --
  65. rP1 EQU $FF00
  66. P1F_5 EQU %00100000 ; P15 out port, set to 0 to get buttons
  67. P1F_4 EQU %00010000 ; P14 out port, set to 0 to get dpad
  68. P1F_3 EQU %00001000 ; P13 in port
  69. P1F_2 EQU %00000100 ; P12 in port
  70. P1F_1 EQU %00000010 ; P11 in port
  71. P1F_0 EQU %00000001 ; P10 in port
  72. P1F_GET_DPAD EQU P1F_5
  73. P1F_GET_BTN EQU P1F_4
  74. P1F_GET_NONE EQU P1F_4 | P1F_5
  75. ; --
  76. ; -- SB ($FF01)
  77. ; -- Serial Transfer Data (R/W)
  78. ; --
  79. rSB EQU $FF01
  80. ; --
  81. ; -- SC ($FF02)
  82. ; -- Serial I/O Control (R/W)
  83. ; --
  84. rSC EQU $FF02
  85. ; --
  86. ; -- DIV ($FF04)
  87. ; -- Divider register (R/W)
  88. ; --
  89. rDIV EQU $FF04
  90. ; --
  91. ; -- TIMA ($FF05)
  92. ; -- Timer counter (R/W)
  93. ; --
  94. rTIMA EQU $FF05
  95. ; --
  96. ; -- TMA ($FF06)
  97. ; -- Timer modulo (R/W)
  98. ; --
  99. rTMA EQU $FF06
  100. ; --
  101. ; -- TAC ($FF07)
  102. ; -- Timer control (R/W)
  103. ; --
  104. rTAC EQU $FF07
  105. TACF_START EQU %00000100
  106. TACF_STOP EQU %00000000
  107. TACF_4KHZ EQU %00000000
  108. TACF_16KHZ EQU %00000011
  109. TACF_65KHZ EQU %00000010
  110. TACF_262KHZ EQU %00000001
  111. ; --
  112. ; -- IF ($FF0F)
  113. ; -- Interrupt Flag (R/W)
  114. ; --
  115. rIF EQU $FF0F
  116. ; --
  117. ; -- AUD1SWEEP/NR10 ($FF10)
  118. ; -- Sweep register (R/W)
  119. ; --
  120. ; -- Bit 6-4 - Sweep Time
  121. ; -- Bit 3 - Sweep Increase/Decrease
  122. ; -- 0: Addition (frequency increases???)
  123. ; -- 1: Subtraction (frequency increases???)
  124. ; -- Bit 2-0 - Number of sweep shift (# 0-7)
  125. ; -- Sweep Time: (n*7.8ms)
  126. ; --
  127. rNR10 EQU $FF10
  128. rAUD1SWEEP EQU rNR10
  129. AUD1SWEEP_UP EQU %00000000
  130. AUD1SWEEP_DOWN EQU %00001000
  131. ; --
  132. ; -- AUD1LEN/NR11 ($FF11)
  133. ; -- Sound length/Wave pattern duty (R/W)
  134. ; --
  135. ; -- Bit 7-6 - Wave Pattern Duty (00:12.5% 01:25% 10:50% 11:75%)
  136. ; -- Bit 5-0 - Sound length data (# 0-63)
  137. ; --
  138. rNR11 EQU $FF11
  139. rAUD1LEN EQU rNR11
  140. ; --
  141. ; -- AUD1ENV/NR12 ($FF12)
  142. ; -- Envelope (R/W)
  143. ; --
  144. ; -- Bit 7-4 - Initial value of envelope
  145. ; -- Bit 3 - Envelope UP/DOWN
  146. ; -- 0: Decrease
  147. ; -- 1: Range of increase
  148. ; -- Bit 2-0 - Number of envelope sweep (# 0-7)
  149. ; --
  150. rNR12 EQU $FF12
  151. rAUD1ENV EQU rNR12
  152. ; --
  153. ; -- AUD1LOW/NR13 ($FF13)
  154. ; -- Frequency low byte (W)
  155. ; --
  156. rNR13 EQU $FF13
  157. rAUD1LOW EQU rNR13
  158. ; --
  159. ; -- AUD1HIGH/NR14 ($FF14)
  160. ; -- Frequency high byte (W)
  161. ; --
  162. ; -- Bit 7 - Initial (when set, sound restarts)
  163. ; -- Bit 6 - Counter/consecutive selection
  164. ; -- Bit 2-0 - Frequency's higher 3 bits
  165. ; --
  166. rNR14 EQU $FF14
  167. rAUD1HIGH EQU rNR14
  168. ; --
  169. ; -- AUD2LEN/NR21 ($FF16)
  170. ; -- Sound Length; Wave Pattern Duty (R/W)
  171. ; --
  172. ; -- see AUD1LEN for info
  173. ; --
  174. rNR21 EQU $FF16
  175. rAUD2LEN EQU rNR21
  176. ; --
  177. ; -- AUD2ENV/NR22 ($FF17)
  178. ; -- Envelope (R/W)
  179. ; --
  180. ; -- see AUD1ENV for info
  181. ; --
  182. rNR22 EQU $FF17
  183. rAUD2ENV EQU rNR22
  184. ; --
  185. ; -- AUD2LOW/NR23 ($FF18)
  186. ; -- Frequency low byte (W)
  187. ; --
  188. rNR23 EQU $FF18
  189. rAUD2LOW EQU rNR23
  190. ; --
  191. ; -- AUD2HIGH/NR24 ($FF19)
  192. ; -- Frequency high byte (W)
  193. ; --
  194. ; -- see AUD1HIGH for info
  195. ; --
  196. rNR24 EQU $FF19
  197. rAUD2HIGH EQU rNR24
  198. ; --
  199. ; -- AUD3ENA/NR30 ($FF1A)
  200. ; -- Sound on/off (R/W)
  201. ; --
  202. ; -- Bit 7 - Sound ON/OFF (1=ON,0=OFF)
  203. ; --
  204. rNR30 EQU $FF1A
  205. rAUD3ENA EQU rNR30
  206. ; --
  207. ; -- AUD3LEN/NR31 ($FF1B)
  208. ; -- Sound length (R/W)
  209. ; --
  210. ; -- Bit 7-0 - Sound length
  211. ; --
  212. rNR31 EQU $FF1B
  213. rAUD3LEN EQU rNR31
  214. ; --
  215. ; -- AUD3LEVEL/NR32 ($FF1C)
  216. ; -- Select output level
  217. ; --
  218. ; -- Bit 6-5 - Select output level
  219. ; -- 00: 0/1 (mute)
  220. ; -- 01: 1/1
  221. ; -- 10: 1/2
  222. ; -- 11: 1/4
  223. ; --
  224. rNR32 EQU $FF1C
  225. rAUD3LEVEL EQU rNR32
  226. ; --
  227. ; -- AUD3LOW/NR33 ($FF1D)
  228. ; -- Frequency low byte (W)
  229. ; --
  230. ; -- see AUD1LOW for info
  231. ; --
  232. rNR33 EQU $FF1D
  233. rAUD3LOW EQU rNR33
  234. ; --
  235. ; -- AUD3HIGH/NR34 ($FF1E)
  236. ; -- Frequency high byte (W)
  237. ; --
  238. ; -- see AUD1HIGH for info
  239. ; --
  240. rNR34 EQU $FF1E
  241. rAUD3HIGH EQU rNR34
  242. ; --
  243. ; -- AUD4LEN/NR41 ($FF20)
  244. ; -- Sound length (R/W)
  245. ; --
  246. ; -- Bit 5-0 - Sound length data (# 0-63)
  247. ; --
  248. rNR41 EQU $FF20
  249. rAUD4LEN EQU rNR41
  250. ; --
  251. ; -- AUD4ENV/NR42 ($FF21)
  252. ; -- Envelope (R/W)
  253. ; --
  254. ; -- see AUD1ENV for info
  255. ; --
  256. rNR42 EQU $FF21
  257. rAUD4ENV EQU rNR42
  258. ; --
  259. ; -- AUD4POLY/NR43 ($FF22)
  260. ; -- Polynomial counter (R/W)
  261. ; --
  262. ; -- Bit 7-4 - Selection of the shift clock frequency of the (scf)
  263. ; -- polynomial counter (0000-1101)
  264. ; -- freq=drf*1/2^scf (not sure)
  265. ; -- Bit 3 - Selection of the polynomial counter's step
  266. ; -- 0: 15 steps
  267. ; -- 1: 7 steps
  268. ; -- Bit 2-0 - Selection of the dividing ratio of frequencies (drf)
  269. ; -- 000: f/4 001: f/8 010: f/16 011: f/24
  270. ; -- 100: f/32 101: f/40 110: f/48 111: f/56 (f=4.194304 Mhz)
  271. ; --
  272. rNR43 EQU $FF22
  273. rAUD4POLY EQU rNR43
  274. ; --
  275. ; -- AUD4GO/NR44 ($FF23)
  276. ; --
  277. ; -- Bit 7 - Inital
  278. ; -- Bit 6 - Counter/consecutive selection
  279. ; --
  280. rNR44 EQU $FF23
  281. rAUD4GO EQU rNR44
  282. ; --
  283. ; -- AUDVOL/NR50 ($FF24)
  284. ; -- Channel control / ON-OFF / Volume (R/W)
  285. ; --
  286. ; -- Bit 7 - Vin->SO2 ON/OFF (Vin??)
  287. ; -- Bit 6-4 - SO2 output level (volume) (# 0-7)
  288. ; -- Bit 3 - Vin->SO1 ON/OFF (Vin??)
  289. ; -- Bit 2-0 - SO1 output level (volume) (# 0-7)
  290. ; --
  291. rNR50 EQU $FF24
  292. rAUDVOL EQU rNR50
  293. AUDVOL_VIN_LEFT EQU %10000000 ; SO2
  294. AUDVOL_VIN_RIGHT EQU %00001000 ; SO1
  295. ; --
  296. ; -- AUDTERM/NR51 ($FF25)
  297. ; -- Selection of Sound output terminal (R/W)
  298. ; --
  299. ; -- Bit 7 - Output sound 4 to SO2 terminal
  300. ; -- Bit 6 - Output sound 3 to SO2 terminal
  301. ; -- Bit 5 - Output sound 2 to SO2 terminal
  302. ; -- Bit 4 - Output sound 1 to SO2 terminal
  303. ; -- Bit 3 - Output sound 4 to SO1 terminal
  304. ; -- Bit 2 - Output sound 3 to SO1 terminal
  305. ; -- Bit 1 - Output sound 2 to SO1 terminal
  306. ; -- Bit 0 - Output sound 0 to SO1 terminal
  307. ; --
  308. rNR51 EQU $FF25
  309. rAUDTERM EQU rNR51
  310. ; SO2
  311. AUDTERM_4_LEFT EQU %10000000
  312. AUDTERM_3_LEFT EQU %01000000
  313. AUDTERM_2_LEFT EQU %00100000
  314. AUDTERM_1_LEFT EQU %00010000
  315. ; SO1
  316. AUDTERM_4_RIGHT EQU %00001000
  317. AUDTERM_3_RIGHT EQU %00000100
  318. AUDTERM_2_RIGHT EQU %00000010
  319. AUDTERM_1_RIGHT EQU %00000001
  320. ; --
  321. ; -- AUDENA/NR52 ($FF26)
  322. ; -- Sound on/off (R/W)
  323. ; --
  324. ; -- Bit 7 - All sound on/off (sets all audio regs to 0!)
  325. ; -- Bit 3 - Sound 4 ON flag (read only)
  326. ; -- Bit 2 - Sound 3 ON flag (read only)
  327. ; -- Bit 1 - Sound 2 ON flag (read only)
  328. ; -- Bit 0 - Sound 1 ON flag (read only)
  329. ; --
  330. rNR52 EQU $FF26
  331. rAUDENA EQU rNR52
  332. AUDENA_ON EQU %10000000
  333. AUDENA_OFF EQU %00000000 ; sets all audio regs to 0!
  334. ; --
  335. ; -- LCDC ($FF40)
  336. ; -- LCD Control (R/W)
  337. ; --
  338. rLCDC EQU $FF40
  339. LCDCF_OFF EQU %00000000 ; LCD Control Operation
  340. LCDCF_ON EQU %10000000 ; LCD Control Operation
  341. LCDCF_WIN9800 EQU %00000000 ; Window Tile Map Display Select
  342. LCDCF_WIN9C00 EQU %01000000 ; Window Tile Map Display Select
  343. LCDCF_WINOFF EQU %00000000 ; Window Display
  344. LCDCF_WINON EQU %00100000 ; Window Display
  345. LCDCF_BG8800 EQU %00000000 ; BG & Window Tile Data Select
  346. LCDCF_BG8000 EQU %00010000 ; BG & Window Tile Data Select
  347. LCDCF_BG9800 EQU %00000000 ; BG Tile Map Display Select
  348. LCDCF_BG9C00 EQU %00001000 ; BG Tile Map Display Select
  349. LCDCF_OBJ8 EQU %00000000 ; OBJ Construction
  350. LCDCF_OBJ16 EQU %00000100 ; OBJ Construction
  351. LCDCF_OBJOFF EQU %00000000 ; OBJ Display
  352. LCDCF_OBJON EQU %00000010 ; OBJ Display
  353. LCDCF_BGOFF EQU %00000000 ; BG Display
  354. LCDCF_BGON EQU %00000001 ; BG Display
  355. ; "Window Character Data Select" follows BG
  356. ; --
  357. ; -- STAT ($FF41)
  358. ; -- LCDC Status (R/W)
  359. ; --
  360. rSTAT EQU $FF41
  361. STATF_LYC EQU %01000000 ; LYC=LY Coincidence (Selectable)
  362. STATF_MODE10 EQU %00100000 ; Mode 10
  363. STATF_MODE01 EQU %00010000 ; Mode 01 (V-Blank)
  364. STATF_MODE00 EQU %00001000 ; Mode 00 (H-Blank)
  365. STATF_LYCF EQU %00000100 ; Coincidence Flag
  366. STATF_HBL EQU %00000000 ; H-Blank
  367. STATF_VBL EQU %00000001 ; V-Blank
  368. STATF_OAM EQU %00000010 ; OAM-RAM is used by system
  369. STATF_LCD EQU %00000011 ; Both OAM and VRAM used by system
  370. STATF_BUSY EQU %00000010 ; When set, VRAM access is unsafe
  371. ; --
  372. ; -- SCY ($FF42)
  373. ; -- Scroll Y (R/W)
  374. ; --
  375. rSCY EQU $FF42
  376. ; --
  377. ; -- SCX ($FF43)
  378. ; -- Scroll X (R/W)
  379. ; --
  380. rSCX EQU $FF43
  381. ; --
  382. ; -- LY ($FF44)
  383. ; -- LCDC Y-Coordinate (R)
  384. ; --
  385. ; -- Values range from 0->153. 144->153 is the VBlank period.
  386. ; --
  387. rLY EQU $FF44
  388. ; --
  389. ; -- LYC ($FF45)
  390. ; -- LY Compare (R/W)
  391. ; --
  392. ; -- When LY==LYC, STATF_LYCF will be set in STAT
  393. ; --
  394. rLYC EQU $FF45
  395. ; --
  396. ; -- DMA ($FF46)
  397. ; -- DMA Transfer and Start Address (W)
  398. ; --
  399. rDMA EQU $FF46
  400. ; --
  401. ; -- BGP ($FF47)
  402. ; -- BG Palette Data (W)
  403. ; --
  404. ; -- Bit 7-6 - Intensity for %11
  405. ; -- Bit 5-4 - Intensity for %10
  406. ; -- Bit 3-2 - Intensity for %01
  407. ; -- Bit 1-0 - Intensity for %00
  408. ; --
  409. rBGP EQU $FF47
  410. ; --
  411. ; -- OBP0 ($FF48)
  412. ; -- Object Palette 0 Data (W)
  413. ; --
  414. ; -- See BGP for info
  415. ; --
  416. rOBP0 EQU $FF48
  417. ; --
  418. ; -- OBP1 ($FF49)
  419. ; -- Object Palette 1 Data (W)
  420. ; --
  421. ; -- See BGP for info
  422. ; --
  423. rOBP1 EQU $FF49
  424. ; --
  425. ; -- WY ($FF4A)
  426. ; -- Window Y Position (R/W)
  427. ; --
  428. ; -- 0 <= WY <= 143
  429. ; -- When WY = 0, the window is displayed from the top edge of the LCD screen.
  430. ; --
  431. rWY EQU $FF4A
  432. ; --
  433. ; -- WX ($FF4B)
  434. ; -- Window X Position (R/W)
  435. ; --
  436. ; -- 7 <= WX <= 166
  437. ; -- When WX = 7, the window is displayed from the left edge of the LCD screen.
  438. ; -- Values of 0-6 and 166 are unreliable due to hardware bugs.
  439. ; --
  440. rWX EQU $FF4B
  441. ; --
  442. ; -- SPEED ($FF4D)
  443. ; -- Select CPU Speed (R/W)
  444. ; --
  445. rKEY1 EQU $FF4D
  446. rSPD EQU rKEY1
  447. KEY1F_DBLSPEED EQU %10000000 ; 0=Normal Speed, 1=Double Speed (R)
  448. KEY1F_PREPARE EQU %00000001 ; 0=No, 1=Prepare (R/W)
  449. ; --
  450. ; -- VBK ($FF4F)
  451. ; -- Select Video RAM Bank (R/W)
  452. ; --
  453. ; -- Bit 0 - Bank Specification (0: Specify Bank 0; 1: Specify Bank 1)
  454. ; --
  455. rVBK EQU $FF4F
  456. ; --
  457. ; -- HDMA1 ($FF51)
  458. ; -- High byte for Horizontal Blanking/General Purpose DMA source address (W)
  459. ; -- CGB Mode Only
  460. ; --
  461. rHDMA1 EQU $FF51
  462. ; --
  463. ; -- HDMA2 ($FF52)
  464. ; -- Low byte for Horizontal Blanking/General Purpose DMA source address (W)
  465. ; -- CGB Mode Only
  466. ; --
  467. rHDMA2 EQU $FF52
  468. ; --
  469. ; -- HDMA3 ($FF53)
  470. ; -- High byte for Horizontal Blanking/General Purpose DMA destination address (W)
  471. ; -- CGB Mode Only
  472. ; --
  473. rHDMA3 EQU $FF53
  474. ; --
  475. ; -- HDMA4 ($FF54)
  476. ; -- Low byte for Horizontal Blanking/General Purpose DMA destination address (W)
  477. ; -- CGB Mode Only
  478. ; --
  479. rHDMA4 EQU $FF54
  480. ; --
  481. ; -- HDMA5 ($FF55)
  482. ; -- Transfer length (in tiles minus 1)/mode/start for Horizontal Blanking, General Purpose DMA (R/W)
  483. ; -- CGB Mode Only
  484. ; --
  485. rHDMA5 EQU $FF55
  486. HDMA5F_MODE_GP EQU %00000000 ; General Purpose DMA (W)
  487. HDMA5F_MODE_HBL EQU %10000000 ; HBlank DMA (W)
  488. ; -- Once DMA has started, use HDMA5F_BUSY to check when the transfer is complete
  489. HDMA5F_BUSY EQU %10000000 ; 0=Busy (DMA still in progress), 1=Transfer complete (R)
  490. ; --
  491. ; -- RP ($FF56)
  492. ; -- Infrared Communications Port (R/W)
  493. ; -- CGB Mode Only
  494. ; --
  495. rRP EQU $FF56
  496. RPF_ENREAD EQU %11000000
  497. RPF_DATAIN EQU %00000010 ; 0=Receiving IR Signal, 1=Normal
  498. RPF_WRITE_HI EQU %00000001
  499. RPF_WRITE_LO EQU %00000000
  500. ; --
  501. ; -- BCPS ($FF68)
  502. ; -- Background Color Palette Specification (R/W)
  503. ; --
  504. rBCPS EQU $FF68
  505. BCPSF_AUTOINC EQU %10000000 ; Auto Increment (0=Disabled, 1=Increment after Writing)
  506. ; --
  507. ; -- BCPD ($FF69)
  508. ; -- Background Color Palette Data (R/W)
  509. ; --
  510. rBCPD EQU $FF69
  511. ; --
  512. ; -- OCPS ($FF6A)
  513. ; -- Object Color Palette Specification (R/W)
  514. ; --
  515. rOCPS EQU $FF6A
  516. OCPSF_AUTOINC EQU %10000000 ; Auto Increment (0=Disabled, 1=Increment after Writing)
  517. ; --
  518. ; -- OCPD ($FF6B)
  519. ; -- Object Color Palette Data (R/W)
  520. ; --
  521. rOCPD EQU $FF6B
  522. ; --
  523. ; -- SMBK/SVBK ($FF70)
  524. ; -- Select Main RAM Bank (R/W)
  525. ; --
  526. ; -- Bit 2-0 - Bank Specification (0,1: Specify Bank 1; 2-7: Specify Banks 2-7)
  527. ; --
  528. rSVBK EQU $FF70
  529. rSMBK EQU rSVBK
  530. ; --
  531. ; -- PCM12 ($FF76)
  532. ; -- Sound channel 1&2 PCM amplitude (R)
  533. ; --
  534. ; -- Bit 7-4 - Copy of sound channel 2's PCM amplitude
  535. ; -- Bit 3-0 - Copy of sound channel 1's PCM amplitude
  536. ; --
  537. rPCM12 EQU $FF76
  538. ; --
  539. ; -- PCM34 ($FF77)
  540. ; -- Sound channel 3&4 PCM amplitude (R)
  541. ; --
  542. ; -- Bit 7-4 - Copy of sound channel 4's PCM amplitude
  543. ; -- Bit 3-0 - Copy of sound channel 3's PCM amplitude
  544. ; --
  545. rPCM34 EQU $FF77
  546. ; --
  547. ; -- IE ($FFFF)
  548. ; -- Interrupt Enable (R/W)
  549. ; --
  550. rIE EQU $FFFF
  551. IEF_HILO EQU %00010000 ; Transition from High to Low of Pin number P10-P13
  552. IEF_SERIAL EQU %00001000 ; Serial I/O transfer end
  553. IEF_TIMER EQU %00000100 ; Timer Overflow
  554. IEF_LCDC EQU %00000010 ; LCDC (see STAT)
  555. IEF_VBLANK EQU %00000001 ; V-Blank
  556. ;***************************************************************************
  557. ;*
  558. ;* Flags common to multiple sound channels
  559. ;*
  560. ;***************************************************************************
  561. ; --
  562. ; -- Square wave duty cycle
  563. ; --
  564. ; -- Can be used with AUD1LEN and AUD2LEN
  565. ; -- See AUD1LEN for more info
  566. ; --
  567. AUDLEN_DUTY_12_5 EQU %00000000 ; 12.5%
  568. AUDLEN_DUTY_25 EQU %01000000 ; 25%
  569. AUDLEN_DUTY_50 EQU %10000000 ; 50%
  570. AUDLEN_DUTY_75 EQU %11000000 ; 75%
  571. ; --
  572. ; -- Audio envelope flags
  573. ; --
  574. ; -- Can be used with AUD1ENV, AUD2ENV, AUD4ENV
  575. ; -- See AUD1ENV for more info
  576. ; --
  577. AUDENV_UP EQU %00001000
  578. AUDENV_DOWN EQU %00000000
  579. ; --
  580. ; -- Audio trigger flags
  581. ; --
  582. ; -- Can be used with AUD1HIGH, AUD2HIGH, AUD3HIGH
  583. ; -- See AUD1HIGH for more info
  584. ; --
  585. AUDHIGH_RESTART EQU %10000000
  586. AUDHIGH_LENGTH_ON EQU %01000000
  587. AUDHIGH_LENGTH_OFF EQU %00000000
  588. ;***************************************************************************
  589. ;*
  590. ;* CPU values on bootup (a=type, b=qualifier)
  591. ;*
  592. ;***************************************************************************
  593. BOOTUP_A_DMG EQU $01 ; Dot Matrix Game
  594. BOOTUP_A_CGB EQU $11 ; Color GameBoy
  595. BOOTUP_A_MGB EQU $FF ; Mini GameBoy (Pocket GameBoy)
  596. ; if a=BOOTUP_A_CGB, bit 0 in b can be checked to determine if real CGB or
  597. ; other system running in GBC mode
  598. BOOTUP_B_CGB EQU %00000000
  599. BOOTUP_B_AGB EQU %00000001 ; GBA, GBA SP, Game Boy Player, or New GBA SP
  600. ;***************************************************************************
  601. ;*
  602. ;* Cart related
  603. ;*
  604. ;***************************************************************************
  605. ; $0143 Color GameBoy compatibility code
  606. CART_COMPATIBLE_DMG EQU $00
  607. CART_COMPATIBLE_DMG_GBC EQU $80
  608. CART_COMPATIBLE_GBC EQU $C0
  609. ; $0146 GameBoy/Super GameBoy indicator
  610. CART_INDICATOR_GB EQU $00
  611. CART_INDICATOR_SGB EQU $03
  612. ; $0147 Cartridge type
  613. CART_ROM EQU $00
  614. CART_ROM_MBC1 EQU $01
  615. CART_ROM_MBC1_RAM EQU $02
  616. CART_ROM_MBC1_RAM_BAT EQU $03
  617. CART_ROM_MBC2 EQU $05
  618. CART_ROM_MBC2_BAT EQU $06
  619. CART_ROM_RAM EQU $08
  620. CART_ROM_RAM_BAT EQU $09
  621. CART_ROM_MMM01 EQU $0B
  622. CART_ROM_MMM01_RAM EQU $0C
  623. CART_ROM_MMM01_RAM_BAT EQU $0D
  624. CART_ROM_MBC3_BAT_RTC EQU $0F
  625. CART_ROM_MBC3_RAM_BAT_RTC EQU $10
  626. CART_ROM_MBC3 EQU $11
  627. CART_ROM_MBC3_RAM EQU $12
  628. CART_ROM_MBC3_RAM_BAT EQU $13
  629. CART_ROM_MBC5 EQU $19
  630. CART_ROM_MBC5_BAT EQU $1A
  631. CART_ROM_MBC5_RAM_BAT EQU $1B
  632. CART_ROM_MBC5_RUMBLE EQU $1C
  633. CART_ROM_MBC5_RAM_RUMBLE EQU $1D
  634. CART_ROM_MBC5_RAM_BAT_RUMBLE EQU $1E
  635. CART_ROM_MBC7_RAM_BAT_GYRO EQU $22
  636. CART_ROM_POCKET_CAMERA EQU $FC
  637. CART_ROM_BANDAI_TAMA5 EQU $FD
  638. CART_ROM_HUDSON_HUC3 EQU $FE
  639. CART_ROM_HUDSON_HUC1 EQU $FF
  640. ; $0148 ROM size
  641. ; these are kilobytes
  642. CART_ROM_32KB EQU $00 ; 2 banks
  643. CART_ROM_64KB EQU $01 ; 4 banks
  644. CART_ROM_128KB EQU $02 ; 8 banks
  645. CART_ROM_256KB EQU $03 ; 16 banks
  646. CART_ROM_512KB EQU $04 ; 32 banks
  647. CART_ROM_1024KB EQU $05 ; 64 banks
  648. CART_ROM_2048KB EQU $06 ; 128 banks
  649. CART_ROM_4096KB EQU $07 ; 256 banks
  650. CART_ROM_8192KB EQU $08 ; 512 banks
  651. CART_ROM_1152KB EQU $52 ; 72 banks
  652. CART_ROM_1280KB EQU $53 ; 80 banks
  653. CART_ROM_1536KB EQU $54 ; 96 banks
  654. ; $0149 SRAM size
  655. ; these are kilobytes
  656. CART_SRAM_NONE EQU 0
  657. CART_SRAM_2KB EQU 1 ; 1 incomplete bank
  658. CART_SRAM_8KB EQU 2 ; 1 bank
  659. CART_SRAM_32KB EQU 3 ; 4 banks
  660. CART_SRAM_128KB EQU 4 ; 16 banks
  661. CART_SRAM_ENABLE EQU $0A
  662. CART_SRAM_DISABLE EQU $00
  663. ; $014A Destination code
  664. CART_DEST_JAPANESE EQU $00
  665. CART_DEST_NON_JAPANESE EQU $01
  666. ;***************************************************************************
  667. ;*
  668. ;* Keypad related
  669. ;*
  670. ;***************************************************************************
  671. PADF_DOWN EQU $80
  672. PADF_UP EQU $40
  673. PADF_LEFT EQU $20
  674. PADF_RIGHT EQU $10
  675. PADF_START EQU $08
  676. PADF_SELECT EQU $04
  677. PADF_B EQU $02
  678. PADF_A EQU $01
  679. PADB_DOWN EQU $7
  680. PADB_UP EQU $6
  681. PADB_LEFT EQU $5
  682. PADB_RIGHT EQU $4
  683. PADB_START EQU $3
  684. PADB_SELECT EQU $2
  685. PADB_B EQU $1
  686. PADB_A EQU $0
  687. ;***************************************************************************
  688. ;*
  689. ;* Screen related
  690. ;*
  691. ;***************************************************************************
  692. SCRN_X EQU 160 ; Width of screen in pixels
  693. SCRN_Y EQU 144 ; Height of screen in pixels
  694. SCRN_X_B EQU 20 ; Width of screen in bytes
  695. SCRN_Y_B EQU 18 ; Height of screen in bytes
  696. SCRN_VX EQU 256 ; Virtual width of screen in pixels
  697. SCRN_VY EQU 256 ; Virtual height of screen in pixels
  698. SCRN_VX_B EQU 32 ; Virtual width of screen in bytes
  699. SCRN_VY_B EQU 32 ; Virtual height of screen in bytes
  700. ;***************************************************************************
  701. ;*
  702. ;* OAM related
  703. ;*
  704. ;***************************************************************************
  705. ; OAM attributes
  706. ; each entry in OAM RAM is 4 bytes (sizeof_OAM_ATTRS)
  707. RSRESET
  708. OAMA_Y RB 1 ; y pos
  709. OAMA_X RB 1 ; x pos
  710. OAMA_TILEID RB 1 ; tile id
  711. OAMA_FLAGS RB 1 ; flags (see below)
  712. sizeof_OAM_ATTRS RB 0
  713. OAM_COUNT EQU 40 ; number of OAM entries in OAM RAM
  714. ; flags
  715. OAMF_PRI EQU %10000000 ; Priority
  716. OAMF_YFLIP EQU %01000000 ; Y flip
  717. OAMF_XFLIP EQU %00100000 ; X flip
  718. OAMF_PAL0 EQU %00000000 ; Palette number; 0,1 (DMG)
  719. OAMF_PAL1 EQU %00010000 ; Palette number; 0,1 (DMG)
  720. OAMF_BANK0 EQU %00000000 ; Bank number; 0,1 (GBC)
  721. OAMF_BANK1 EQU %00001000 ; Bank number; 0,1 (GBC)
  722. OAMF_PALMASK EQU %00000111 ; Palette (GBC)
  723. OAMB_PRI EQU 7 ; Priority
  724. OAMB_YFLIP EQU 6 ; Y flip
  725. OAMB_XFLIP EQU 5 ; X flip
  726. OAMB_PAL1 EQU 4 ; Palette number; 0,1 (DMG)
  727. OAMB_BANK1 EQU 3 ; Bank number; 0,1 (GBC)
  728. ;*
  729. ;* Nintendo scrolling logo
  730. ;* (Code won't work on a real GameBoy)
  731. ;* (if next lines are altered.)
  732. NINTENDO_LOGO : MACRO
  733. DB $CE,$ED,$66,$66,$CC,$0D,$00,$0B,$03,$73,$00,$83,$00,$0C,$00,$0D
  734. DB $00,$08,$11,$1F,$88,$89,$00,$0E,$DC,$CC,$6E,$E6,$DD,$DD,$D9,$99
  735. DB $BB,$BB,$67,$63,$6E,$0E,$EC,$CC,$DD,$DC,$99,$9F,$BB,$B9,$33,$3E
  736. ENDM
  737. ENDC ;HARDWARE_INC