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494 lines
14 KiB
494 lines
14 KiB
#ifndef GBSDK_HARDWARE_H
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#define GBSDK_HARDWARE_H
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// Register for reading joy pad info. (R/W)
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static volatile __sfr __at(0x00) rP1;
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#define P1_5 0b00100000 // P15 out port, set to 0 to get buttons
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#define P1_4 0b00010000 // P14 out port, set to 0 to get dpad
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#define P1_3 0b00001000 // P13 in port
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#define P1_2 0b00000100 // P12 in port
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#define P1_1 0b00000010 // P11 in port
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#define P1_0 0b00000001 // P10 in port
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#define P1_GET_DPAD P1_5
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#define P1_GET_BTN P1_4
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#define P1_GET_NONE (P1_4 | P1_5)
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// Serial Transfer Data (R/W)
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static volatile __sfr __at(0x01) rSB;
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// Serial I/O Control (R/W)
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static volatile __sfr __at(0x02) rSC;
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// Divider register (R/W)
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static volatile __sfr __at(0x04) rDIV;
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// Timer counter (R/W)
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static volatile __sfr __at(0x05) rTIMA;
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// Timer modulo (R/W)
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static volatile __sfr __at(0x06) rTMA;
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// Timer control (R/W)
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static volatile __sfr __at(0x07) rTAC;
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#define TAC_START 0b00000100
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#define TAC_STOP 0b00000000
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#define TAC_4KHZ 0b00000000
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#define TAC_16KHZ 0b00000011
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#define TAC_65KHZ 0b00000010
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#define TAC_262KHZ 0b00000001
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// Interrupt Flag (R/W)
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static volatile __sfr __at(0x0F) rIF;
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// AUD1SWEEP/NR10 ($FF10)
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// Sweep register (R/W)
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//
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// Bit 6-4 - Sweep Time
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// Bit 3 - Sweep Increase/Decrease
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// 0: Addition (frequency increases???)
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// 1: Subtraction (frequency increases???)
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// Bit 2-0 - Number of sweep shift (# 0-7)
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// Sweep Time: (n*7.8ms)
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static volatile __sfr __at(0x10) rNR10;
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#define rAUD1SWEEP rNR10
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#define AUD1SWEEP_UP 0b00000000
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#define AUD1SWEEP_DOWN 0b00001000
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// AUD1LEN/NR11 ($FF11)
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// Sound length/Wave pattern duty (R/W)
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//
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// Bit 7-6 - Wave Pattern Duty (00:12.5% 01:25% 10:50% 11:75%)
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// Bit 5-0 - Sound length data (# 0-63)
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static volatile __sfr __at(0x11) rNR11;
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#define rAUD1LEN rNR11
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// AUD1ENV/NR12 ($FF12)
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// Envelope (R/W)
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//
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// Bit 7-4 - Initial value of envelope
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// Bit 3 - Envelope UP/DOWN
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// 0: Decrease
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// 1: Range of increase
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// Bit 2-0 - Number of envelope sweep (# 0-7)
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static volatile __sfr __at(0x12) rNR12;
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#define rAUD1ENV rNR12
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// AUD1LOW/NR13 ($FF13)
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// Frequency low byte (W)
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static volatile __sfr __at(0x13) rNR13;
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#define rAUD1LOW rNR13
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// AUD1HIGH/NR14 ($FF14)
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// Frequency high byte (W)
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//
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// Bit 7 - Initial (when set, sound restarts)
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// Bit 6 - Counter/consecutive selection
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// Bit 2-0 - Frequency's higher 3 bits
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static volatile __sfr __at(0x14) rNR14;
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#define rAUD1HIGH rNR14
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// AUD2LEN/NR21 ($FF16)
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// Sound Length; Wave Pattern Duty (R/W)
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//
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// see AUD1LEN for info
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static volatile __sfr __at(0x16) rNR21;
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#define rAUD2LEN rNR21
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// AUD2ENV/NR22 ($FF17)
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// Envelope (R/W)
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//
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// see AUD1ENV for info
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static volatile __sfr __at(0x17) rNR22;
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#define rAUD2ENV rNR22
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// AUD2LOW/NR23 ($FF18)
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// Frequency low byte (W)
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static volatile __sfr __at(0x18) rNR23;
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#define rAUD2LOW rNR23
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// AUD2HIGH/NR24 ($FF19)
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// Frequency high byte (W)
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//
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// see AUD1HIGH for info
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static volatile __sfr __at(0x19) rNR24;
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#define rAUD2HIGH rNR24
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// AUD3ENA/NR30 ($FF1A)
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// Sound on/off (R/W)
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//
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// Bit 7 - Sound ON/OFF (1=ON,0=OFF)
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static volatile __sfr __at(0x1A) rNR30;
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#define rAUD3ENA rNR30
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// AUD3LEN/NR31 ($FF1B)
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// Sound length (R/W)
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//
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// Bit 7-0 - Sound length
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static volatile __sfr __at(0x1B) rNR31;
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#define rAUD3LEN rNR31
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// AUD3LEVEL/NR32 ($FF1C)
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// Select output level
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//
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// Bit 6-5 - Select output level
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// 00: 0/1 (mute)
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// 01: 1/1
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// 10: 1/2
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// 11: 1/4
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static volatile __sfr __at(0x1C) rNR32;
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#define rAUD3LEVEL rNR32
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// AUD3LOW/NR33 ($FF1D)
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// Frequency low byte (W)
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//
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// see AUD1LOW for info
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static volatile __sfr __at(0x1D) rNR33;
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#define rAUD3LOW rNR33
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// AUD3HIGH/NR34 ($FF1E)
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// Frequency high byte (W)
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//
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// see AUD1HIGH for info
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static volatile __sfr __at(0x1E) rNR34;
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#define rAUD3HIGH rNR34
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// AUD4LEN/NR41 ($FF20)
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// Sound length (R/W)
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//
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// Bit 5-0 - Sound length data (# 0-63)
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static volatile __sfr __at(0x20) rNR41;
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#define rAUD4LEN rNR41
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// AUD4ENV/NR42 ($FF21)
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// Envelope (R/W)
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//
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// see AUD1ENV for info
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static volatile __sfr __at(0x21) rNR42;
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#define rAUD4ENV rNR42
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// AUD4POLY/NR43 ($FF22)
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// Polynomial counter (R/W)
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//
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// Bit 7-4 - Selection of the shift clock frequency of the (scf)
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// polynomial counter (0000-1101)
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// freq=drf*1/2^scf (not sure)
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// Bit 3 - Selection of the polynomial counter's step
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// 0: 15 steps
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// 1: 7 steps
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// Bit 2-0 - Selection of the dividing ratio of frequencies (drf)
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// 000: f/4 001: f/8 010: f/16 011: f/24
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// 100: f/32 101: f/40 110: f/48 111: f/56 (f=4.194304 Mhz)
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static volatile __sfr __at(0x22) rNR43;
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#define rAUD4POLY rNR43
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// AUD4GO/NR44 ($FF23)
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//
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// Bit 7 - Inital
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// Bit 6 - Counter/consecutive selection
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static volatile __sfr __at(0x23) rNR44;
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#define rAUD4GO rNR44
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// AUDVOL/NR50 ($FF24)
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// Channel control / ON-OFF / Volume (R/W)
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//
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// Bit 7 - Vin->SO2 ON/OFF (Vin??)
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// Bit 6-4 - SO2 output level (volume) (# 0-7)
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// Bit 3 - Vin->SO1 ON/OFF (Vin??)
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// Bit 2-0 - SO1 output level (volume) (# 0-7)
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static volatile __sfr __at(0x24) rNR50;
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#define rAUDVOL rNR50
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#define AUDVOL_VIN_LEFT 0b10000000 // SO2
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#define AUDVOL_VIN_RIGHT 0b00001000 // SO1
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// AUDTERM/NR51 ($FF25)
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// Selection of Sound output terminal (R/W)
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//
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// Bit 7 - Output sound 4 to SO2 terminal
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// Bit 6 - Output sound 3 to SO2 terminal
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// Bit 5 - Output sound 2 to SO2 terminal
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// Bit 4 - Output sound 1 to SO2 terminal
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// Bit 3 - Output sound 4 to SO1 terminal
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// Bit 2 - Output sound 3 to SO1 terminal
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// Bit 1 - Output sound 2 to SO1 terminal
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// Bit 0 - Output sound 0 to SO1 terminal
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static volatile __sfr __at(0x25) rNR51;
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#define rAUDTERM rNR51
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// SO2
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#define AUDTERM_4_LEFT 0b10000000
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#define AUDTERM_3_LEFT 0b01000000
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#define AUDTERM_2_LEFT 0b00100000
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#define AUDTERM_1_LEFT 0b00010000
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// SO1
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#define AUDTERM_4_RIGHT 0b00001000
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#define AUDTERM_3_RIGHT 0b00000100
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#define AUDTERM_2_RIGHT 0b00000010
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#define AUDTERM_1_RIGHT 0b00000001
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// AUDENA/NR52 ($FF26)
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// Sound on/off (R/W)
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//
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// Bit 7 - All sound on/off (sets all audio regs to 0!)
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// Bit 3 - Sound 4 ON flag (read only)
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// Bit 2 - Sound 3 ON flag (read only)
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// Bit 1 - Sound 2 ON flag (read only)
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// Bit 0 - Sound 1 ON flag (read only)
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static volatile __sfr __at(0x26) rNR52;
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#define rAUDENA rNR52
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#define AUDENA_ON 0b10000000
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#define AUDENA_OFF 0b00000000 // sets all audio regs to 0!
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// LCDC ($FF40)
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// LCD Control (R/W)
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static volatile __sfr __at(0x40) rLCDC;
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#define LCDC_OFF 0b00000000 // LCD Control Operation
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#define LCDC_ON 0b10000000 // LCD Control Operation
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#define LCDC_WIN9800 0b00000000 // Window Tile Map Display Select
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#define LCDC_WIN9C00 0b01000000 // Window Tile Map Display Select
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#define LCDC_WINOFF 0b00000000 // Window Display
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#define LCDC_WINON 0b00100000 // Window Display
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#define LCDC_BG8800 0b00000000 // BG & Window Tile Data Select
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#define LCDC_BG8000 0b00010000 // BG & Window Tile Data Select
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#define LCDC_BG9800 0b00000000 // BG Tile Map Display Select
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#define LCDC_BG9C00 0b00001000 // BG Tile Map Display Select
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#define LCDC_OBJ8 0b00000000 // OBJ Construction
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#define LCDC_OBJ16 0b00000100 // OBJ Construction
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#define LCDC_OBJOFF 0b00000000 // OBJ Display
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#define LCDC_OBJON 0b00000010 // OBJ Display
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#define LCDC_BGOFF 0b00000000 // BG Display
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#define LCDC_BGON 0b00000001 // BG Display
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// STAT ($FF41)
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// LCDC Status (R/W)
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static volatile __sfr __at(0x41) rSTAT;
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#define STAT_LYC 0b01000000 // LYC=LY Coincidence (Selectable)
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#define STAT_MODE10 0b00100000 // Mode 10
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#define STAT_MODE01 0b00010000 // Mode 01 (V-Blank)
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#define STAT_MODE00 0b00001000 // Mode 00 (H-Blank)
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#define STAT_LYCF 0b00000100 // Coincidence Flag
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#define STAT_HBL 0b00000000 // H-Blank
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#define STAT_VBL 0b00000001 // V-Blank
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#define STAT_OAM 0b00000010 // OAM-RAM is used by system
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#define STAT_LCD 0b00000011 // Both OAM and VRAM used by system
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#define STAT_BUSY 0b00000010 // When set, VRAM access is unsafe
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// SCY ($FF42)
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// Scroll Y (R/W)
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static volatile __sfr __at(0x42) rSCY;
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// SCX ($FF43)
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// Scroll X (R/W)
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static volatile __sfr __at(0x43) rSCX;
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// LY ($FF44)
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// LCDC Y-Coordinate (R)
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//
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// Values range from 0->153. 144->153 is the VBlank period.
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static volatile __sfr __at(0x44) rLY;
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// LYC ($FF45)
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// LY Compare (R/W)
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//
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// When LY==LYC, STATF_LYCF will be set in STAT
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static volatile __sfr __at(0x45) rLYC;
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// DMA ($FF46)
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// DMA Transfer and Start Address (W)
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static volatile __sfr __at(0x46) rDMA;
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// BGP ($FF47)
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// BG Palette Data (W)
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//
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// Bit 7-6 - Intensity for %11
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// Bit 5-4 - Intensity for %10
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// Bit 3-2 - Intensity for %01
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// Bit 1-0 - Intensity for %00
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static volatile __sfr __at(0x47) rBGP;
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// OBP0 ($FF48)
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// Object Palette 0 Data (W)
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//
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// See BGP for info
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static volatile __sfr __at(0x48) rOBP0;
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// OBP1 ($FF49)
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// Object Palette 1 Data (W)
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//
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// See BGP for info
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static volatile __sfr __at(0x49) rOBP1;
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// WY ($FF4A)
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// Window Y Position (R/W)
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//
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// 0 <= WY <= 143
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// When WY = 0, the window is displayed from the top edge of the LCD screen.
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static volatile __sfr __at(0x4A) rWY;
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// WX ($FF4B)
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// Window X Position (R/W)
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//
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// 7 <= WX <= 166
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// When WX = 7, the window is displayed from the left edge of the LCD screen.
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// Values of 0-6 and 166 are unreliable due to hardware bugs.
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static volatile __sfr __at(0x4B) rWX;
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#if CGB
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// SPEED ($FF4D)
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// Select CPU Speed (R/W)
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static volatile __sfr __at(0x4D) rKEY1;
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#define rSPD rKEY1
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#define KEY1_DBLSPEED 0b10000000 // 0=Normal Speed, 1=Double Speed (R)
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#define KEY1_PREPARE 0b00000001 // 0=No, 1=Prepare (R/W)
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// VBK ($FF4F)
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// Select Video RAM Bank (R/W)
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//
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// Bit 0 - Bank Specification (0: Specify Bank 0; 1: Specify Bank 1)
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static volatile __sfr __at(0x4F) rVBK;
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// HDMA1 ($FF51)
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// High byte for Horizontal Blanking/General Purpose DMA source address (W)
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static volatile __sfr __at(0x51) rHDMA1;
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// HDMA2 ($FF52)
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// Low byte for Horizontal Blanking/General Purpose DMA source address (W)
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static volatile __sfr __at(0x52) rHDMA2;
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// HDMA3 ($FF53)
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// High byte for Horizontal Blanking/General Purpose DMA destination address (W)
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static volatile __sfr __at(0x53) rHDMA3;
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// HDMA4 ($FF54)
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// Low byte for Horizontal Blanking/General Purpose DMA destination address (W)
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static volatile __sfr __at(0x54) rHDMA4;
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// HDMA5 ($FF55)
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// Transfer length (in tiles minus 1)/mode/start for Horizontal Blanking, General Purpose DMA (R/W)
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static volatile __sfr __at(0x55) rHDMA5;
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#define HDMA5_MODE_GP 0b00000000 // General Purpose DMA (W)
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#define HDMA5_MODE_HBL 0b10000000 // HBlank DMA (W)
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// Once DMA has started, use HDMA5F_BUSY to check when the transfer is complete
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#define HDMA5_BUSY 0b10000000 // 0=Busy (DMA still in progress), 1=Transfer complete (R)
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// RP ($FF56)
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// Infrared Communications Port (R/W)
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static volatile __sfr __at(0x56) rRP;
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#define RP_ENREAD 0b11000000
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#define RP_DATAIN 0b00000010 // 0=Receiving IR Signal, 1=Normal
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#define RP_WRITE_HI 0b00000001
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#define RP_WRITE_LO 0b00000000
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// BCPS ($FF68)
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// Background Color Palette Specification (R/W)
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static volatile __sfr __at(0x68) rBCPS;
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#define BCPS_AUTOINC 0b10000000 // Auto Increment (0=Disabled, 1=Increment after Writing)
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// BCPD ($FF69)
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// Background Color Palette Data (R/W)
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static volatile __sfr __at(0x69) rBCPD;
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// OCPS ($FF6A)
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// Object Color Palette Specification (R/W)
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static volatile __sfr __at(0x6A) rOCPS;
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#define OCPS_AUTOINC 0b10000000 // Auto Increment (0=Disabled, 1=Increment after Writing)
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// OCPD ($FF6B)
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// Object Color Palette Data (R/W)
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static volatile __sfr __at(0x6B) rOCPD;
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// SMBK/SVBK ($FF70)
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// Select Main RAM Bank (R/W)
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//
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// Bit 2-0 - Bank Specification (0,1: Specify Bank 1; 2-7: Specify Banks 2-7)
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static volatile __sfr __at(0x70) rSVBK;
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#define rSMBK rSVBK
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// PCM12 ($FF76)
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// Sound channel 1&2 PCM amplitude (R)
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//
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// Bit 7-4 - Copy of sound channel 2's PCM amplitude
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// Bit 3-0 - Copy of sound channel 1's PCM amplitude
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static volatile __sfr __at(0x76) rPCM12;
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// PCM34 ($FF77)
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// Sound channel 3&4 PCM amplitude (R)
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//
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// Bit 7-4 - Copy of sound channel 4's PCM amplitude
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// Bit 3-0 - Copy of sound channel 3's PCM amplitude
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static volatile __sfr __at(0x77) rPCM34;
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#endif //CGB
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// IE ($FFFF)
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// Interrupt Enable (R/W)
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static volatile __sfr __at(0xFF) rIE;
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#define IE_HILO 0b00010000 // Transition from High to Low of Pin number P10-P13
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#define IE_SERIAL 0b00001000 // Serial I/O transfer end
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#define IE_TIMER 0b00000100 // Timer Overflow
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#define IE_LCDC 0b00000010 // LCDC (see STAT)
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#define IE_VBLANK 0b00000001 // V-Blank
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/***************************************************************************
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*
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* Flags common to multiple sound channels
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*
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***************************************************************************/
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// Square wave duty cycle
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//
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// Can be used with AUD1LEN and AUD2LEN
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// See AUD1LEN for more info
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#define AUDLEN_DUTY_12_5 0b00000000 // 12.5%
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#define AUDLEN_DUTY_25 0b01000000 // 25%
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#define AUDLEN_DUTY_50 0b10000000 // 50%
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#define AUDLEN_DUTY_75 0b11000000 // 75%
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// Audio envelope flags
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//
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// Can be used with AUD1ENV, AUD2ENV, AUD4ENV
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// See AUD1ENV for more info
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#define AUDENV_UP 0b00001000
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#define AUDENV_DOWN 0b00000000
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// Audio trigger flags
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//
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// Can be used with AUD1HIGH, AUD2HIGH, AUD3HIGH
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// See AUD1HIGH for more info
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#define AUDHIGH_RESTART 0b10000000
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#define AUDHIGH_LENGTH_ON 0b01000000
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#define AUDHIGH_LENGTH_OFF 0b00000000
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// Shared bits between the OAM attributes and the CGB background attributes.
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#define ATTR_PRI 0b10000000
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#define ATTR_YFLIP 0b01000000
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#define ATTR_XFLIP 0b00100000
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#define ATTR_PAL0 0b00000000
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#define ATTR_PAL1 0b00010000
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#if CGB
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#define ATTR_BANK0 0b00000000
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#define ATTR_BANK1 0b00001000
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#define ATTR_PALMASK 0b00000111
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#endif
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// Defines for specific instructions
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#define HALT() __asm__("halt")
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#define DISABLE_INTERRUPTS() __asm__("di")
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#define ENABLE_INTERRUPTS() __asm__("ei")
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#endif
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