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@ -1,10 +1,11 @@ |
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#include "insn.h" |
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#include "log.h" |
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#include "cpu.h" |
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#include <stddef.h> |
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#include <stdio.h> |
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#include "cpu.h" |
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#include "log.h" |
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#define TABLE_SIZE 0x34 |
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void insn_lw(cpu_t *cpu, uint32_t insn); |
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@ -26,37 +27,32 @@ static cpu_insn_handler secondary_insn_handler[TABLE_SIZE] = {NULL}; |
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#define OP2(insn) BITS(insn, 0, 6) |
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#define IMM(insn) BITS(insn, 0, 16) |
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void insn_execute(cpu_t *cpu, uint32_t insn) |
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{ |
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const op_primary_t op = OP(insn); |
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void insn_execute(cpu_t *cpu, uint32_t insn) { |
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const op_primary_t op = OP(insn); |
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if (op == SPECIAL) |
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{ |
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const op_secondary_t op2 = OP2(insn); |
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if (op == SPECIAL) { |
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const op_secondary_t op2 = OP2(insn); |
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if (op2 > TABLE_SIZE || secondary_insn_handler[op2] == NULL) |
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{ |
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fatal("Unsupported instruction: insn=%08x, op=%02x, op2=%02x", insn, |
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op, op2); |
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} |
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if (op2 > TABLE_SIZE || secondary_insn_handler[op2] == NULL) { |
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fatal("Unsupported instruction: insn=%08x, op=%02x, op2=%02x", insn, |
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op, op2); |
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} |
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secondary_insn_handler[op2](cpu, insn); |
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} |
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secondary_insn_handler[op2](cpu, insn); |
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} |
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if (op > TABLE_SIZE || primary_insn_handler[op] == NULL) |
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{ |
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fatal("Unsupported instruction: insn=%08x, op=%02x", insn, op); |
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} |
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if (op > TABLE_SIZE || primary_insn_handler[op] == NULL) { |
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fatal("Unsupported instruction: insn=%08x, op=%02x", insn, op); |
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} |
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primary_insn_handler[op](cpu, insn); |
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primary_insn_handler[op](cpu, insn); |
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} |
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void insn_lw(cpu_t *cpu, uint32_t insn) |
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{ |
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const uint8_t rs = RS(insn); |
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const uint8_t rt = RT(insn); |
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const uint16_t imm = IMM(insn); |
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void insn_lw(cpu_t *cpu, uint32_t insn) { |
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const uint8_t rs = RS(insn); |
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const uint8_t rt = RT(insn); |
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const uint16_t imm = IMM(insn); |
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debug("LW %s, [%s + %x]", REG_NAMES[rt], REG_NAMES[rs], imm); |
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cpu->regs[rt] = cpu_read32(cpu, cpu->regs[rs] + imm); |
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debug("LW %s, [%s + %x]", REG_NAMES[rt], REG_NAMES[rs], imm); |
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cpu->regs[rt] = cpu_read32(cpu, cpu->regs[rs] + imm); |
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} |