Implement ADDU/ADDIU

src/insn.c

@@ -54,7 +54,7 @@ void insn_lw(cpu_t *cpu, uint32_t insn) {
 }
 
 void insn_srl(cpu_t *cpu, uint32_t insn) {
-    const uint8_t rd = RT(insn);
+    const uint8_t rd = RD(insn);
     const uint8_t rt = RT(insn);
     const uint8_t imm5 = IMM5(insn);
 
@@ -62,10 +62,30 @@ void insn_srl(cpu_t *cpu, uint32_t insn) {
     cpu->regs[rd] = cpu->regs[rt] >> imm5;
 }
 
+void insn_addu(cpu_t *cpu, uint32_t insn) {
+    const uint8_t rd = RD(insn);
+    const uint8_t rs = RS(insn);
+    const uint8_t rt = RT(insn);
+
+    debug("ADDU %s, %s, %s", REG_NAMES[rd], REG_NAMES[rs], REG_NAMES[rt]);
+    cpu->regs[rd] = cpu->regs[rs] + cpu->regs[rt];
+}
+
+void insn_addiu(cpu_t *cpu, uint32_t insn) {
+    const uint8_t rt = RT(insn);
+    const uint8_t rs = RS(insn);
+    const int16_t imm = (int16_t)IMM(insn);
+
+    debug("ADDIU %s, %s, %x", REG_NAMES[rt], REG_NAMES[rs], imm);
+    cpu->regs[rt] = cpu->regs[rs] + imm;
+}
+
 static cpu_insn_handler primary_insn_handler[TABLE_SIZE] = {
     [LW] = insn_lw,
+    [ADDIU] = insn_addiu,
 };
 
 static cpu_insn_handler secondary_insn_handler[TABLE_SIZE] = {
+    [ADDU] = insn_addu,
     [SRL] = insn_srl,
 };