From ba72ba2dd7a3cb1c8d413297d46a855af75fc71d Mon Sep 17 00:00:00 2001
From: Forest Belton <65484+forestbelton@users.noreply.github.com>
Date: Sat, 26 Jun 2021 19:00:17 -0400
Subject: [PATCH] Implement SRL instruction

---
 src/insn.c | 30 +++++++++++++++++++++---------
 1 file changed, 21 insertions(+), 9 deletions(-)

diff --git a/src/insn.c b/src/insn.c
index 51b9707..b02fd95 100644
--- a/src/insn.c
+++ b/src/insn.c
@@ -8,14 +8,6 @@
 
 #define TABLE_SIZE 0x34
 
-void insn_lw(cpu_t *cpu, uint32_t insn);
-
-static cpu_insn_handler primary_insn_handler[TABLE_SIZE] = {
-    [LW] = insn_lw,
-};
-
-static cpu_insn_handler secondary_insn_handler[TABLE_SIZE] = {NULL};
-
 #define BITS(x, start, len) (((x) >> (start)) & ((1 << (len)) - 1))
 
 #define OP(insn) BITS(insn, 26, 6)
@@ -27,6 +19,9 @@ static cpu_insn_handler secondary_insn_handler[TABLE_SIZE] = {NULL};
 #define OP2(insn) BITS(insn, 0, 6)
 #define IMM(insn) BITS(insn, 0, 16)
 
+static cpu_insn_handler primary_insn_handler[TABLE_SIZE];
+static cpu_insn_handler secondary_insn_handler[TABLE_SIZE];
+
 void insn_execute(cpu_t *cpu, uint32_t insn) {
     const op_primary_t op = OP(insn);
 
@@ -49,10 +44,27 @@ void insn_execute(cpu_t *cpu, uint32_t insn) {
 }
 
 void insn_lw(cpu_t *cpu, uint32_t insn) {
-    const uint8_t rs = RS(insn);
     const uint8_t rt = RT(insn);
+    const uint8_t rs = RS(insn);
     const uint16_t imm = IMM(insn);
 
     debug("LW %s, [%s + %x]", REG_NAMES[rt], REG_NAMES[rs], imm);
     cpu->regs[rt] = cpu_read32(cpu, cpu->regs[rs] + imm);
 }
+
+void insn_srl(cpu_t *cpu, uint32_t insn) {
+    const uint8_t rd = RT(insn);
+    const uint8_t rt = RT(insn);
+    const uint8_t imm5 = IMM5(insn);
+
+    debug("SRL %s, %s, %u", REG_NAMES[rd], REG_NAMES[rt], imm5);
+    cpu->regs[rd] = cpu->regs[rt] >> imm5;
+}
+
+static cpu_insn_handler primary_insn_handler[TABLE_SIZE] = {
+    [LW] = insn_lw,
+};
+
+static cpu_insn_handler secondary_insn_handler[TABLE_SIZE] = {
+    [SRL] = insn_srl,
+};