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@ -89,6 +89,15 @@ void insn_sw(cpu_t *cpu, uint32_t insn) { |
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cpu_write32(cpu, cpu->regs[rt], imm + cpu->regs[rs]); |
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cpu_write32(cpu, cpu->regs[rt], imm + cpu->regs[rs]); |
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} |
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} |
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void insn_sll(cpu_t *cpu, uint32_t insn) { |
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const uint8_t rd = RD(insn); |
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const uint8_t rt = RT(insn); |
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const uint8_t imm5 = IMM5(insn); |
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debug("SLL %s, %s, %u", REG_NAMES[rd], REG_NAMES[rt], imm5); |
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cpu->regs[rd] = cpu->regs[rt] << imm5; |
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} |
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static cpu_insn_handler primary_insn_handler[TABLE_SIZE] = { |
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static cpu_insn_handler primary_insn_handler[TABLE_SIZE] = { |
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[LW] = insn_lw, |
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[LW] = insn_lw, |
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[ADDIU] = insn_addiu, |
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[ADDIU] = insn_addiu, |
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@ -96,6 +105,7 @@ static cpu_insn_handler primary_insn_handler[TABLE_SIZE] = { |
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}; |
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}; |
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static cpu_insn_handler secondary_insn_handler[TABLE_SIZE] = { |
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static cpu_insn_handler secondary_insn_handler[TABLE_SIZE] = { |
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[SLL] = insn_sll, |
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[ADDU] = insn_addu, |
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[ADDU] = insn_addu, |
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[SRL] = insn_srl, |
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[SRL] = insn_srl, |
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}; |
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}; |