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129 lines
3.5 KiB
129 lines
3.5 KiB
#include "insn.h"
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#include <stddef.h>
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#include <stdio.h>
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#include "cpu.h"
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#include "log.h"
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#define TABLE_SIZE 0x34
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#define BITS(x, start, len) (((x) >> (start)) & ((1 << (len)) - 1))
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#define OP(insn) BITS(insn, 26, 6)
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#define RS(insn) BITS(insn, 21, 5)
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#define RT(insn) BITS(insn, 16, 5)
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#define RD(insn) BITS(insn, 11, 5)
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#define COMMENT(insn) BITS(insn, 6, 20)
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#define IMM5(insn) BITS(insn, 6, 5)
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#define OP2(insn) BITS(insn, 0, 6)
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#define IMM(insn) BITS(insn, 0, 16)
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static cpu_insn_handler primary_insn_handler[TABLE_SIZE];
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static cpu_insn_handler secondary_insn_handler[TABLE_SIZE];
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void insn_execute(cpu_t *cpu, uint32_t insn) {
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const op_primary_t op = OP(insn);
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if (op == SPECIAL) {
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const op_secondary_t op2 = OP2(insn);
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if (op2 > TABLE_SIZE || secondary_insn_handler[op2] == NULL) {
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fatal("Unsupported instruction: insn=%08x, op=%02x, op2=%02x", insn,
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op, op2);
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}
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secondary_insn_handler[op2](cpu, insn);
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return;
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}
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if (op > TABLE_SIZE || primary_insn_handler[op] == NULL) {
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fatal("Unsupported instruction: insn=%08x, op=%02x", insn, op);
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}
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primary_insn_handler[op](cpu, insn);
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}
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void insn_lw(cpu_t *cpu, uint32_t insn) {
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const uint8_t rt = RT(insn);
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const uint8_t rs = RS(insn);
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const uint16_t imm = IMM(insn);
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debug("LW %s, [%s + %x]", REG_NAMES[rt], REG_NAMES[rs], imm);
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cpu->regs[rt] = cpu_read32(cpu, cpu->regs[rs] + imm);
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}
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void insn_srl(cpu_t *cpu, uint32_t insn) {
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const uint8_t rd = RD(insn);
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const uint8_t rt = RT(insn);
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const uint8_t imm5 = IMM5(insn);
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debug("SRL %s, %s, %u", REG_NAMES[rd], REG_NAMES[rt], imm5);
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cpu->regs[rd] = cpu->regs[rt] >> imm5;
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}
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void insn_addu(cpu_t *cpu, uint32_t insn) {
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const uint8_t rd = RD(insn);
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const uint8_t rs = RS(insn);
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const uint8_t rt = RT(insn);
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debug("ADDU %s, %s, %s", REG_NAMES[rd], REG_NAMES[rs], REG_NAMES[rt]);
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cpu->regs[rd] = cpu->regs[rs] + cpu->regs[rt];
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}
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void insn_addiu(cpu_t *cpu, uint32_t insn) {
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const uint8_t rt = RT(insn);
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const uint8_t rs = RS(insn);
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const int16_t imm = (int16_t)IMM(insn);
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debug("ADDIU %s, %s, %x", REG_NAMES[rt], REG_NAMES[rs], imm);
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cpu->regs[rt] = cpu->regs[rs] + imm;
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}
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void insn_sw(cpu_t *cpu, uint32_t insn) {
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const uint8_t rt = RT(insn);
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const uint8_t rs = RS(insn);
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const uint16_t imm = IMM(insn);
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debug("SW %s, [%s + %x]", REG_NAMES[rt], REG_NAMES[rt], imm);
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cpu_write32(cpu, cpu->regs[rt], imm + cpu->regs[rs]);
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}
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void insn_sll(cpu_t *cpu, uint32_t insn) {
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const uint8_t rd = RD(insn);
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const uint8_t rt = RT(insn);
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const uint8_t imm5 = IMM5(insn);
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debug("SLL %s, %s, %u", REG_NAMES[rd], REG_NAMES[rt], imm5);
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cpu->regs[rd] = cpu->regs[rt] << imm5;
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}
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void insn_beq(cpu_t *cpu, uint32_t insn) {
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const uint8_t rs = RS(insn);
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const uint8_t rt = RT(insn);
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const int16_t imm = IMM(insn);
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debug("BEQ %s, %s, %d", REG_NAMES[rs], REG_NAMES[rt], imm);
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if (cpu->regs[rs] == cpu->regs[rt]) {
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cpu->pc += imm * 4;
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}
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}
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void insn_lui(cpu_t *cpu, uint32_t insn) {
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const uint8_t rt = RT(insn);
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const uint16_t imm = IMM(insn);
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debug("LUI %s, %x", REG_NAMES[rt], imm);
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cpu->regs[rt] = imm << 16;
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}
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static cpu_insn_handler primary_insn_handler[TABLE_SIZE] = {
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[BEQ] = insn_beq, [LW] = insn_lw, [LUI] = insn_lui,
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[ADDIU] = insn_addiu, [SW] = insn_sw,
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};
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static cpu_insn_handler secondary_insn_handler[TABLE_SIZE] = {
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[SLL] = insn_sll,
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[ADDU] = insn_addu,
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[SRL] = insn_srl,
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};
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