|
|
@ -98,10 +98,28 @@ void insn_sll(cpu_t *cpu, uint32_t insn) { |
|
|
|
cpu->regs[rd] = cpu->regs[rt] << imm5; |
|
|
|
} |
|
|
|
|
|
|
|
void insn_beq(cpu_t *cpu, uint32_t insn) { |
|
|
|
const uint8_t rs = RS(insn); |
|
|
|
const uint8_t rt = RT(insn); |
|
|
|
const int16_t imm = IMM(insn); |
|
|
|
|
|
|
|
debug("BEQ %s, %s, %d", REG_NAMES[rs], REG_NAMES[rt], imm); |
|
|
|
if (cpu->regs[rs] == cpu->regs[rt]) { |
|
|
|
cpu->pc += imm * 4; |
|
|
|
} |
|
|
|
} |
|
|
|
|
|
|
|
void insn_lui(cpu_t *cpu, uint32_t insn) { |
|
|
|
const uint8_t rt = RT(insn); |
|
|
|
const uint16_t imm = IMM(insn); |
|
|
|
|
|
|
|
debug("LUI %s, %x", REG_NAMES[rt], imm); |
|
|
|
cpu->regs[rt] = imm << 16; |
|
|
|
} |
|
|
|
|
|
|
|
static cpu_insn_handler primary_insn_handler[TABLE_SIZE] = { |
|
|
|
[LW] = insn_lw, |
|
|
|
[ADDIU] = insn_addiu, |
|
|
|
[SW] = insn_sw, |
|
|
|
[BEQ] = insn_beq, [LW] = insn_lw, [LUI] = insn_lui, |
|
|
|
[ADDIU] = insn_addiu, [SW] = insn_sw, |
|
|
|
}; |
|
|
|
|
|
|
|
static cpu_insn_handler secondary_insn_handler[TABLE_SIZE] = { |
|
|
|